qemu/hw/riscv
Michael Clark b6aa6cedf4
RISC-V: Add missing free for plic_hart_config
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-17 13:02:24 -07:00
..
Makefile.objs RISC-V Build Infrastructure 2018-03-07 08:30:28 +13:00
riscv_hart.c riscv_hart: Fix crash when introspecting the device 2018-07-19 09:05:48 -07:00
riscv_htif.c hw: Do not include "exec/address-spaces.h" if it is not necessary 2018-06-01 14:15:10 +02:00
sifive_clint.c RISC-V: Allow setting and clearing multiple irqs 2018-10-17 13:02:09 -07:00
sifive_e.c Drop "qemu:" prefix from error_report() arguments 2018-09-24 17:13:07 +02:00
sifive_plic.c RISC-V: Allow setting and clearing multiple irqs 2018-10-17 13:02:09 -07:00
sifive_prci.c SiFive RISC-V PRCI Block 2018-03-07 08:30:28 +13:00
sifive_test.c SiFive RISC-V Test Finisher 2018-03-07 08:30:28 +13:00
sifive_u.c Drop "qemu:" prefix from error_report() arguments 2018-09-24 17:13:07 +02:00
sifive_uart.c SiFive RISC-V UART Device 2018-03-07 08:30:28 +13:00
spike.c Error reporting & miscellaneous patches for 2018-09-24 2018-09-25 11:37:39 +01:00
virt.c RISC-V: Add missing free for plic_hart_config 2018-10-17 13:02:24 -07:00