LIU Zhiwei b655dc7cd9 target/riscv: Don't save pc when exception return ... As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-3-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-01-21 15:52:57 +10:00
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trans_privileged.c.inc	target/riscv: Don't save pc when exception return	2022-01-21 15:52:57 +10:00
trans_rva.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvb.c.inc	target/riscv: support for 128-bit arithmetic instructions	2022-01-08 15:46:10 +10:00
trans_rvd.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvf.c.inc	target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions	2021-10-28 14:39:23 +10:00
trans_rvh.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvi.c.inc	target/riscv: modification of the trans_csrxx for 128-bit support	2022-01-08 15:46:10 +10:00
trans_rvm.c.inc	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
trans_rvv.c.inc	target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns	2022-01-21 15:52:56 +10:00
trans_rvzfh.c.inc	target/riscv: zfh: implement zfhmin extension	2021-12-20 14:51:36 +10:00