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b5fd8fa345
qemu/target-tricore
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Bastian Koppelmann b5fd8fa345 target-tricore: Add missing 1.6 insn of BOL opcode format 
Some of the 1.6 ISA instructions were still missing. So let's add them.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21 18:35:28 +00:00
..
cpu-qom.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
cpu.c target-tricore: Make TRICORE_FEATURES implying others. 2014-12-10 11:13:45 +00:00
cpu.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
csfr.def target-tricore: Add instructions of RLC opcode format 2014-12-10 11:13:45 +00:00
helper.c target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
helper.h target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode 2014-12-21 18:35:16 +00:00
Makefile.objs
op_helper.c target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode 2014-12-21 18:35:16 +00:00
translate.c target-tricore: Add missing 1.6 insn of BOL opcode format 2014-12-21 18:35:28 +00:00
tricore-defs.h
tricore-opcodes.h target-tricore: Add missing 1.6 insn of BOL opcode format 2014-12-21 18:35:28 +00:00