dc5e072188
PPC TCG supports SMT CPU configurations for non-hypervisor state, so permit POWER8-10 pseries machines to enable SMT. This requires PIR and TIR be set, because that's how sibling thread matching is done by TCG. spapr's nested-HV capability does not currently coexist with SMT, so that combination is prohibited (interestingly somewhat analogous to LPAR-per-core mode on real hardware which also does not support KVM). Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: Also test smp_threads when checking for POWER8 CPU and above ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
405 lines
12 KiB
C
405 lines
12 KiB
C
/*
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* sPAPR CPU core device, acts as container of CPU thread devices.
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*
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* Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "hw/cpu/core.h"
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#include "hw/ppc/spapr_cpu_core.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "target/ppc/cpu.h"
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#include "hw/ppc/spapr.h"
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#include "qapi/error.h"
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#include "sysemu/cpus.h"
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#include "sysemu/kvm.h"
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#include "target/ppc/kvm_ppc.h"
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#include "hw/ppc/ppc.h"
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#include "target/ppc/mmu-hash64.h"
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#include "target/ppc/power8-pmu.h"
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#include "sysemu/numa.h"
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#include "sysemu/reset.h"
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#include "sysemu/hw_accel.h"
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#include "qemu/error-report.h"
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static void spapr_reset_vcpu(PowerPCCPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
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target_ulong lpcr;
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SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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cpu_reset(cs);
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/*
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* "PowerPC Processor binding to IEEE 1275" defines the initial MSR state
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* as 32bit (MSR_SF=0) in "8.2.1. Initial Register Values".
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*/
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env->msr &= ~(1ULL << MSR_SF);
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env->spr[SPR_HIOR] = 0;
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lpcr = env->spr[SPR_LPCR];
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/* Set emulated LPCR to not send interrupts to hypervisor. Note that
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* under KVM, the actual HW LPCR will be set differently by KVM itself,
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* the settings below ensure proper operations with TCG in absence of
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* a real hypervisor.
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*
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* Disable Power-saving mode Exit Cause exceptions for the CPU, so
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* we don't get spurious wakups before an RTAS start-cpu call.
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* For the same reason, set PSSCR_EC.
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*/
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lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
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lpcr |= LPCR_LPES0 | LPCR_LPES1;
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env->spr[SPR_PSSCR] |= PSSCR_EC;
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ppc_store_lpcr(cpu, lpcr);
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/* Set a full AMOR so guest can use the AMR as it sees fit */
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env->spr[SPR_AMOR] = 0xffffffffffffffffull;
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spapr_cpu->vpa_addr = 0;
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spapr_cpu->slb_shadow_addr = 0;
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spapr_cpu->slb_shadow_size = 0;
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spapr_cpu->dtl_addr = 0;
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spapr_cpu->dtl_size = 0;
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spapr_caps_cpu_apply(spapr, cpu);
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kvm_check_mmu(cpu, &error_fatal);
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spapr_irq_cpu_intc_reset(spapr, cpu);
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}
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void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
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target_ulong r1, target_ulong r3,
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target_ulong r4)
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{
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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CPUPPCState *env = &cpu->env;
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env->nip = nip;
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env->gpr[1] = r1;
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env->gpr[3] = r3;
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env->gpr[4] = r4;
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kvmppc_set_reg_ppc_online(cpu, 1);
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CPU(cpu)->halted = 0;
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/* Enable Power-saving mode Exit Cause exceptions */
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ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
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}
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/*
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* Return the sPAPR CPU core type for @model which essentially is the CPU
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* model specified with -cpu cmdline option.
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*/
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const char *spapr_get_cpu_core_type(const char *cpu_type)
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{
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int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
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char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
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len, cpu_type);
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ObjectClass *oc = object_class_by_name(core_type);
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g_free(core_type);
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if (!oc) {
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return NULL;
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}
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return object_class_get_name(oc);
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}
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static bool slb_shadow_needed(void *opaque)
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{
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SpaprCpuState *spapr_cpu = opaque;
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return spapr_cpu->slb_shadow_addr != 0;
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}
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static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
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.name = "spapr_cpu/vpa/slb_shadow",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = slb_shadow_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState),
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VMSTATE_UINT64(slb_shadow_size, SpaprCpuState),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool dtl_needed(void *opaque)
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{
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SpaprCpuState *spapr_cpu = opaque;
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return spapr_cpu->dtl_addr != 0;
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}
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static const VMStateDescription vmstate_spapr_cpu_dtl = {
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.name = "spapr_cpu/vpa/dtl",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = dtl_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(dtl_addr, SpaprCpuState),
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VMSTATE_UINT64(dtl_size, SpaprCpuState),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool vpa_needed(void *opaque)
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{
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SpaprCpuState *spapr_cpu = opaque;
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return spapr_cpu->vpa_addr != 0;
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}
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static const VMStateDescription vmstate_spapr_cpu_vpa = {
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.name = "spapr_cpu/vpa",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = vpa_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(vpa_addr, SpaprCpuState),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription * []) {
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&vmstate_spapr_cpu_slb_shadow,
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&vmstate_spapr_cpu_dtl,
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NULL
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}
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};
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static const VMStateDescription vmstate_spapr_cpu_state = {
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.name = "spapr_cpu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription * []) {
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&vmstate_spapr_cpu_vpa,
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NULL
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}
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};
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static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
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{
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CPUPPCState *env = &cpu->env;
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if (!sc->pre_3_0_migration) {
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vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
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}
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spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu);
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cpu_ppc_tb_free(env);
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qdev_unrealize(DEVICE(cpu));
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}
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/*
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* Called when CPUs are hot-plugged.
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*/
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static void spapr_cpu_core_reset(DeviceState *dev)
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{
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CPUCore *cc = CPU_CORE(dev);
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SpaprCpuCore *sc = SPAPR_CPU_CORE(dev);
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int i;
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for (i = 0; i < cc->nr_threads; i++) {
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spapr_reset_vcpu(sc->threads[i]);
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}
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}
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/*
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* Called by the machine reset.
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*/
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static void spapr_cpu_core_reset_handler(void *opaque)
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{
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spapr_cpu_core_reset(opaque);
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}
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static void spapr_delete_vcpu(PowerPCCPU *cpu)
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{
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SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
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cpu->machine_data = NULL;
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g_free(spapr_cpu);
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object_unparent(OBJECT(cpu));
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}
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static void spapr_cpu_core_unrealize(DeviceState *dev)
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{
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SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
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CPUCore *cc = CPU_CORE(dev);
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int i;
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for (i = 0; i < cc->nr_threads; i++) {
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if (sc->threads[i]) {
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/*
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* Since this we can get here from the error path of
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* spapr_cpu_core_realize(), make sure we only unrealize
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* vCPUs that have already been realized.
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*/
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if (object_property_get_bool(OBJECT(sc->threads[i]), "realized",
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&error_abort)) {
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spapr_unrealize_vcpu(sc->threads[i], sc);
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}
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spapr_delete_vcpu(sc->threads[i]);
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}
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}
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g_free(sc->threads);
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qemu_unregister_reset(spapr_cpu_core_reset_handler, sc);
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}
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static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
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SpaprCpuCore *sc, int thread_index, Error **errp)
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{
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CPUPPCState *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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if (!qdev_realize(DEVICE(cpu), NULL, errp)) {
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return false;
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}
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cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
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kvmppc_set_papr(cpu);
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env->spr_cb[SPR_PIR].default_value = cs->cpu_index;
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env->spr_cb[SPR_TIR].default_value = thread_index;
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/* Set time-base frequency to 512 MHz. vhyp must be set first. */
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cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
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if (spapr_irq_cpu_intc_create(spapr, cpu, errp) < 0) {
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qdev_unrealize(DEVICE(cpu));
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return false;
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}
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if (!sc->pre_3_0_migration) {
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vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
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cpu->machine_data);
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}
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return true;
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}
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static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
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{
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SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
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CPUCore *cc = CPU_CORE(sc);
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g_autoptr(Object) obj = NULL;
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g_autofree char *id = NULL;
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CPUState *cs;
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PowerPCCPU *cpu;
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obj = object_new(scc->cpu_type);
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cs = CPU(obj);
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cpu = POWERPC_CPU(obj);
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/*
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* All CPUs start halted. CPU0 is unhalted from the machine level reset code
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* and the rest are explicitly started up by the guest using an RTAS call.
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*/
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cs->start_powered_off = true;
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cs->cpu_index = cc->core_id + i;
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if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) {
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return NULL;
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}
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cpu->node_id = sc->node_id;
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id = g_strdup_printf("thread[%d]", i);
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object_property_add_child(OBJECT(sc), id, obj);
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cpu->machine_data = g_new0(SpaprCpuState, 1);
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return cpu;
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}
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static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
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{
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/* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
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* tries to add a sPAPR CPU core to a non-pseries machine.
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*/
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SpaprMachineState *spapr =
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(SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
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TYPE_SPAPR_MACHINE);
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SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
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CPUCore *cc = CPU_CORE(OBJECT(dev));
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int i;
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if (!spapr) {
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error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
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return;
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}
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qemu_register_reset(spapr_cpu_core_reset_handler, sc);
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sc->threads = g_new0(PowerPCCPU *, cc->nr_threads);
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for (i = 0; i < cc->nr_threads; i++) {
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sc->threads[i] = spapr_create_vcpu(sc, i, errp);
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if (!sc->threads[i] ||
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!spapr_realize_vcpu(sc->threads[i], spapr, sc, i, errp)) {
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spapr_cpu_core_unrealize(dev);
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return;
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}
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}
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}
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static Property spapr_cpu_core_properties[] = {
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DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
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DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration,
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false),
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DEFINE_PROP_END_OF_LIST()
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};
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static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
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dc->realize = spapr_cpu_core_realize;
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dc->unrealize = spapr_cpu_core_unrealize;
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dc->reset = spapr_cpu_core_reset;
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device_class_set_props(dc, spapr_cpu_core_properties);
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scc->cpu_type = data;
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}
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#define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
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{ \
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.parent = TYPE_SPAPR_CPU_CORE, \
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.class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
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.class_init = spapr_cpu_core_class_init, \
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.name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \
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}
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static const TypeInfo spapr_cpu_core_type_infos[] = {
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{
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.name = TYPE_SPAPR_CPU_CORE,
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.parent = TYPE_CPU_CORE,
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.abstract = true,
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.instance_size = sizeof(SpaprCpuCore),
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.class_size = sizeof(SpaprCpuCoreClass),
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},
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DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
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DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"),
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DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
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#ifdef CONFIG_KVM
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DEFINE_SPAPR_CPU_CORE_TYPE("host"),
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#endif
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};
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DEFINE_TYPES(spapr_cpu_core_type_infos)
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