qemu/tests/tcg/xtensa/vectors.S
Max Filippov f68774ccd8 tests/tcg/xtensa: only generate defined exception handlers
Don't generate handlers for IRQ levels that are not defined for the CPU
or for window overflow/underflow exceptions for configs w/o windowed
registers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17 11:09:04 -07:00

56 lines
974 B
ArmAsm

#include "core-isa.h"
.macro vector name
.section .vector.\name
j 1f
.section .vector.\name\().text
1:
wsr a2, excsave1
movi a2, handler_\name
l32i a2, a2, 0
beqz a2, 1f
jx a2
1:
movi a3, 1b
movi a2, 1
simcall
.align 4
.global handler_\name
handler_\name\(): .word 0
.endm
#if XCHAL_HAVE_WINDOWED
vector window_overflow_4
vector window_overflow_8
vector window_overflow_12
vector window_underflow_4
vector window_underflow_8
vector window_underflow_12
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
vector level2
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3
vector level3
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4
vector level4
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5
vector level5
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6
vector level6
#endif
#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7
vector level7
#endif
vector kernel
vector user
vector double