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Peter Maydell 152be6de91 The first RISC-V PR for the 5.2 window. 
This includes:
  - NaNBox fixes
  - Vector extension improvements
  - a L2 cache controller
  - PMP fixes
  - Upgrade to OpenSBI v0.8 and the generic platform
  - Fixes for the Ibex PLIC
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200821-1' into staging

The first RISC-V PR for the 5.2 window.

This includes:
 - NaNBox fixes
 - Vector extension improvements
 - a L2 cache controller
 - PMP fixes
 - Upgrade to OpenSBI v0.8 and the generic platform
 - Fixes for the Ibex PLIC

# gpg: Signature made Sat 22 Aug 2020 06:38:18 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200821-1:
  hw/intc: ibex_plic: Honour source priorities
  hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines
  hw/intc: ibex_plic: Update the pending irqs
  target/riscv: Change the TLB page size depends on PMP entries.
  target/riscv: Fix the translation of physical address
  gitlab-ci/opensbi: Update GitLab CI to build generic platform
  hw/riscv: spike: Change the default bios to use generic platform image
  hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
  roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware
  roms/opensbi: Upgrade from v0.7 to v0.8
  configure: Create symbolic links for pc-bios/*.elf files
  riscv: Fix bug in setting pmpcfg CSR for RISCV64
  hw/riscv: sifive_u: Add a dummy L2 cache controller device
  target/riscv: check before allocating TCG temps
  target/riscv: Clean up fmv.w.x
  target/riscv: Check nanboxed inputs in trans_rvf.inc.c
  target/riscv: Check nanboxed inputs to fp helpers
  target/riscv: Generate nanboxed results from trans_rvf.inc.c
  target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
  target/riscv: Generate nanboxed results from fp helpers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-08-23 11:38:52 +01:00
..
authz
block block: Add support to warn on backing file change without format 2020-07-14 15:18:59 +02:00
chardev chardev: Reduce "char-mux.h" scope, rename it "chardev-internal.h" 2020-07-13 11:59:47 +04:00
crypto firmware (and crypto) patches 2020-07-09 20:01:43 +01:00
disas target/avr: Register AVR support with the rest of QEMU 2020-07-11 11:02:05 +02:00
exec meson: rename .inc.h files to .h.inc 2020-08-21 06:18:35 -04:00
fpu target/i386: floatx80: avoid compound literals in static initializers 2020-07-27 09:40:16 +01:00
hw The first RISC-V PR for the 5.2 window. 2020-08-23 11:38:52 +01:00
io io/task: Move 'qom/object.h' header to source 2020-06-10 12:09:37 -04:00
libdecnumber
migration migration/colo: Use ram_block_discard_disable() 2020-07-02 05:54:59 -04:00
monitor hmp: Implement qom-get HMP command 2020-06-01 18:44:27 +01:00
net hw/net: Added plen fix for IPv6 2020-07-21 21:30:39 +08:00
qapi qapi/error: Check format string argument in error_*prepend() 2020-07-24 15:03:09 +02:00
qemu meson: infrastructure for building emulators 2020-08-21 06:30:17 -04:00
qom qom: Document object_get_canonical_path() returns malloced string 2020-07-21 16:23:43 +02:00
scsi
standard-headers Linux headers: update 2020-06-18 12:13:36 +02:00
sysemu accel/xen: Fix xen_enabled() behavior on target-agnostic objects 2020-08-04 10:21:35 +01:00
tcg meson: rename included C source files to .c.inc 2020-08-21 06:18:30 -04:00
ui Remove the CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE switch 2020-07-13 11:40:52 +02:00
user trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
elf.h hw/avr: Add support for loading ELF/raw binaries 2020-07-11 11:02:05 +02:00
glib-compat.h
qemu-common.h qemu-common: Document qemu_find_file() 2020-07-21 16:13:04 +02:00
qemu-io.h
trace-tcg.h