qemu/target
Peter Maydell b42ba4ea43 target/xtensa: Make use of 'segment' in pptlb helper less confusing
Coverity gets confused about the use of the 'segment' variable in the
pptlb helper function: it thinks that we can take a code path where
we first initialize it:
  unsigned segment = XTENSA_MPU_PROBE_B;  // 0x40000000
and then use that value as a shift count:
  } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) {

In fact this isn't possible, beacuse xtensa_mpu_lookup() is passed
'&segment', and it uses that as an output value, which it will always
set if it returns nonzero.  But the way the code is currently written
is confusing to a human reader as well as to Coverity.

Instead of initializing 'segment' at the top of the function with a
value that's only used in the "nhits == 0" code path, use the
constant value directly in that code path, and don't initialize
segment.  This matches the way we use xtensa_mpu_lookup() in its
other callsites in get_physical_addr_mpu().

Resolves: Coverity CID 1547589

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Message-id: 20240723151454.1396826-1-peter.maydell@linaro.org
2024-07-29 16:58:14 +01:00
..
alpha target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
arm target/arm: Ignore SMCR_EL2.LEN and SVCR_EL2.LEN if EL2 is not enabled 2024-07-29 16:56:46 +01:00
avr target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
cris target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
hexagon target/hexagon/imported/mmvec: Fix superfluous trailing semicolon 2024-07-17 14:04:15 +03:00
hppa target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
i386 Add support for RAPL MSRs in KVM/Qemu 2024-07-22 19:19:37 +02:00
loongarch target/loongarch: Fix helper_lddir() a CID INTEGER_OVERFLOW issue 2024-07-24 16:52:18 +08:00
m68k target/m68k: Restrict semihosting to TCG 2024-07-22 09:38:08 +01:00
microblaze target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
mips target/mips: Restrict semihosting to TCG 2024-07-22 09:38:10 +01:00
openrisc target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
ppc target/ppc: Remove includes from mmu-book3s-v3.h 2024-07-26 09:51:34 +10:00
riscv accel/tcg: Export set/clear_helper_retaddr 2024-07-23 15:19:39 +10:00
rx target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
s390x accel/tcg: Export set/clear_helper_retaddr 2024-07-23 15:19:39 +10:00
sh4 target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation 2024-07-11 11:41:34 +01:00
sparc sparc/ldst_helper: make range overlap check more readable 2024-07-23 20:30:36 +02:00
tricore target/tricore: Use unsigned types for bitops in helper_eq_b() 2024-07-29 16:57:27 +01:00
xtensa target/xtensa: Make use of 'segment' in pptlb helper less confusing 2024-07-29 16:58:14 +01:00
Kconfig meson: make target endianneess available to Kconfig 2024-05-03 15:47:47 +02:00
meson.build exec: Expose 'target_page.h' API to user emulation 2024-04-26 15:28:11 +02:00