a9ad9e73a7
Allwinner System-on-Chips usually contain a Real Time Clock (RTC) for non-volatile system date and time keeping. This commit adds a generic Allwinner RTC device that supports the RTC devices found in Allwinner SoC family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc). The following RTC functionality and features are implemented: * Year-Month-Day read/write * Hour-Minute-Second read/write * General Purpose storage The following boards are extended with the RTC device: * Cubieboard (hw/arm/cubieboard.c) * Orange Pi PC (hw/arm/orangepi.c) Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-13-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
412 lines
13 KiB
C
412 lines
13 KiB
C
/*
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* Allwinner Real Time Clock emulation
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*
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* Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu-common.h"
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#include "hw/qdev-properties.h"
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#include "hw/rtc/allwinner-rtc.h"
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#include "trace.h"
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/* RTC registers */
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enum {
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REG_LOSC = 1, /* Low Oscillator Control */
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REG_YYMMDD, /* RTC Year-Month-Day */
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REG_HHMMSS, /* RTC Hour-Minute-Second */
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REG_ALARM1_WKHHMMSS, /* Alarm1 Week Hour-Minute-Second */
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REG_ALARM1_EN, /* Alarm1 Enable */
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REG_ALARM1_IRQ_EN, /* Alarm1 IRQ Enable */
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REG_ALARM1_IRQ_STA, /* Alarm1 IRQ Status */
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REG_GP0, /* General Purpose Register 0 */
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REG_GP1, /* General Purpose Register 1 */
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REG_GP2, /* General Purpose Register 2 */
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REG_GP3, /* General Purpose Register 3 */
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/* sun4i registers */
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REG_ALARM1_DDHHMMSS, /* Alarm1 Day Hour-Minute-Second */
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REG_CPUCFG, /* CPU Configuration Register */
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/* sun6i registers */
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REG_LOSC_AUTOSTA, /* LOSC Auto Switch Status */
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REG_INT_OSC_PRE, /* Internal OSC Clock Prescaler */
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REG_ALARM0_COUNTER, /* Alarm0 Counter */
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REG_ALARM0_CUR_VLU, /* Alarm0 Counter Current Value */
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REG_ALARM0_ENABLE, /* Alarm0 Enable */
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REG_ALARM0_IRQ_EN, /* Alarm0 IRQ Enable */
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REG_ALARM0_IRQ_STA, /* Alarm0 IRQ Status */
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REG_ALARM_CONFIG, /* Alarm Config */
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REG_LOSC_OUT_GATING, /* LOSC Output Gating Register */
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REG_GP4, /* General Purpose Register 4 */
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REG_GP5, /* General Purpose Register 5 */
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REG_GP6, /* General Purpose Register 6 */
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REG_GP7, /* General Purpose Register 7 */
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REG_RTC_DBG, /* RTC Debug Register */
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REG_GPL_HOLD_OUT, /* GPL Hold Output Register */
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REG_VDD_RTC, /* VDD RTC Regulate Register */
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REG_IC_CHARA, /* IC Characteristics Register */
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};
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/* RTC register flags */
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enum {
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REG_LOSC_YMD = (1 << 7),
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REG_LOSC_HMS = (1 << 8),
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};
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/* RTC sun4i register map (offset to name) */
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const uint8_t allwinner_rtc_sun4i_regmap[] = {
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[0x0000] = REG_LOSC,
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[0x0004] = REG_YYMMDD,
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[0x0008] = REG_HHMMSS,
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[0x000C] = REG_ALARM1_DDHHMMSS,
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[0x0010] = REG_ALARM1_WKHHMMSS,
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[0x0014] = REG_ALARM1_EN,
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[0x0018] = REG_ALARM1_IRQ_EN,
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[0x001C] = REG_ALARM1_IRQ_STA,
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[0x0020] = REG_GP0,
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[0x0024] = REG_GP1,
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[0x0028] = REG_GP2,
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[0x002C] = REG_GP3,
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[0x003C] = REG_CPUCFG,
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};
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/* RTC sun6i register map (offset to name) */
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const uint8_t allwinner_rtc_sun6i_regmap[] = {
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[0x0000] = REG_LOSC,
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[0x0004] = REG_LOSC_AUTOSTA,
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[0x0008] = REG_INT_OSC_PRE,
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[0x0010] = REG_YYMMDD,
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[0x0014] = REG_HHMMSS,
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[0x0020] = REG_ALARM0_COUNTER,
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[0x0024] = REG_ALARM0_CUR_VLU,
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[0x0028] = REG_ALARM0_ENABLE,
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[0x002C] = REG_ALARM0_IRQ_EN,
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[0x0030] = REG_ALARM0_IRQ_STA,
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[0x0040] = REG_ALARM1_WKHHMMSS,
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[0x0044] = REG_ALARM1_EN,
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[0x0048] = REG_ALARM1_IRQ_EN,
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[0x004C] = REG_ALARM1_IRQ_STA,
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[0x0050] = REG_ALARM_CONFIG,
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[0x0060] = REG_LOSC_OUT_GATING,
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[0x0100] = REG_GP0,
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[0x0104] = REG_GP1,
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[0x0108] = REG_GP2,
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[0x010C] = REG_GP3,
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[0x0110] = REG_GP4,
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[0x0114] = REG_GP5,
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[0x0118] = REG_GP6,
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[0x011C] = REG_GP7,
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[0x0170] = REG_RTC_DBG,
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[0x0180] = REG_GPL_HOLD_OUT,
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[0x0190] = REG_VDD_RTC,
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[0x01F0] = REG_IC_CHARA,
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};
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static bool allwinner_rtc_sun4i_read(AwRtcState *s, uint32_t offset)
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{
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/* no sun4i specific registers currently implemented */
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return false;
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}
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static bool allwinner_rtc_sun4i_write(AwRtcState *s, uint32_t offset,
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uint32_t data)
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{
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/* no sun4i specific registers currently implemented */
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return false;
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}
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static bool allwinner_rtc_sun6i_read(AwRtcState *s, uint32_t offset)
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{
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const AwRtcClass *c = AW_RTC_GET_CLASS(s);
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switch (c->regmap[offset]) {
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case REG_GP4: /* General Purpose Register 4 */
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case REG_GP5: /* General Purpose Register 5 */
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case REG_GP6: /* General Purpose Register 6 */
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case REG_GP7: /* General Purpose Register 7 */
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return true;
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default:
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break;
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}
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return false;
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}
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static bool allwinner_rtc_sun6i_write(AwRtcState *s, uint32_t offset,
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uint32_t data)
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{
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const AwRtcClass *c = AW_RTC_GET_CLASS(s);
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switch (c->regmap[offset]) {
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case REG_GP4: /* General Purpose Register 4 */
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case REG_GP5: /* General Purpose Register 5 */
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case REG_GP6: /* General Purpose Register 6 */
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case REG_GP7: /* General Purpose Register 7 */
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return true;
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default:
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break;
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}
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return false;
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}
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static uint64_t allwinner_rtc_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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AwRtcState *s = AW_RTC(opaque);
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const AwRtcClass *c = AW_RTC_GET_CLASS(s);
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uint64_t val = 0;
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if (offset >= c->regmap_size) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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}
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if (!c->regmap[offset]) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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}
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switch (c->regmap[offset]) {
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case REG_LOSC: /* Low Oscillator Control */
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val = s->regs[REG_LOSC];
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s->regs[REG_LOSC] &= ~(REG_LOSC_YMD | REG_LOSC_HMS);
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break;
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case REG_YYMMDD: /* RTC Year-Month-Day */
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case REG_HHMMSS: /* RTC Hour-Minute-Second */
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case REG_GP0: /* General Purpose Register 0 */
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case REG_GP1: /* General Purpose Register 1 */
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case REG_GP2: /* General Purpose Register 2 */
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case REG_GP3: /* General Purpose Register 3 */
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val = s->regs[c->regmap[offset]];
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break;
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default:
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if (!c->read(s, offset)) {
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
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__func__, (uint32_t)offset);
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}
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val = s->regs[c->regmap[offset]];
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break;
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}
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trace_allwinner_rtc_read(offset, val);
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return val;
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}
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static void allwinner_rtc_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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AwRtcState *s = AW_RTC(opaque);
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const AwRtcClass *c = AW_RTC_GET_CLASS(s);
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if (offset >= c->regmap_size) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return;
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}
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if (!c->regmap[offset]) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
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__func__, (uint32_t)offset);
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return;
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}
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trace_allwinner_rtc_write(offset, val);
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switch (c->regmap[offset]) {
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case REG_YYMMDD: /* RTC Year-Month-Day */
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s->regs[REG_YYMMDD] = val;
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s->regs[REG_LOSC] |= REG_LOSC_YMD;
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break;
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case REG_HHMMSS: /* RTC Hour-Minute-Second */
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s->regs[REG_HHMMSS] = val;
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s->regs[REG_LOSC] |= REG_LOSC_HMS;
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break;
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case REG_GP0: /* General Purpose Register 0 */
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case REG_GP1: /* General Purpose Register 1 */
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case REG_GP2: /* General Purpose Register 2 */
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case REG_GP3: /* General Purpose Register 3 */
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s->regs[c->regmap[offset]] = val;
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break;
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default:
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if (!c->write(s, offset, val)) {
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
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__func__, (uint32_t)offset);
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}
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break;
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}
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}
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static const MemoryRegionOps allwinner_rtc_ops = {
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.read = allwinner_rtc_read,
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.write = allwinner_rtc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl.min_access_size = 4,
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};
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static void allwinner_rtc_reset(DeviceState *dev)
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{
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AwRtcState *s = AW_RTC(dev);
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struct tm now;
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/* Clear registers */
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memset(s->regs, 0, sizeof(s->regs));
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/* Get current datetime */
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qemu_get_timedate(&now, 0);
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/* Set RTC with current datetime */
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if (s->base_year > 1900) {
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s->regs[REG_YYMMDD] = ((now.tm_year + 1900 - s->base_year) << 16) |
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((now.tm_mon + 1) << 8) |
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now.tm_mday;
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s->regs[REG_HHMMSS] = (((now.tm_wday + 6) % 7) << 29) |
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(now.tm_hour << 16) |
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(now.tm_min << 8) |
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now.tm_sec;
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}
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}
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static void allwinner_rtc_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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AwRtcState *s = AW_RTC(obj);
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/* Memory mapping */
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memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_rtc_ops, s,
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TYPE_AW_RTC, 1 * KiB);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription allwinner_rtc_vmstate = {
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.name = "allwinner-rtc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AwRtcState, AW_RTC_REGS_NUM),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property allwinner_rtc_properties[] = {
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DEFINE_PROP_INT32("base-year", AwRtcState, base_year, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void allwinner_rtc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = allwinner_rtc_reset;
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dc->vmsd = &allwinner_rtc_vmstate;
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device_class_set_props(dc, allwinner_rtc_properties);
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}
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static void allwinner_rtc_sun4i_init(Object *obj)
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{
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AwRtcState *s = AW_RTC(obj);
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s->base_year = 2010;
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}
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static void allwinner_rtc_sun4i_class_init(ObjectClass *klass, void *data)
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{
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AwRtcClass *arc = AW_RTC_CLASS(klass);
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arc->regmap = allwinner_rtc_sun4i_regmap;
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arc->regmap_size = sizeof(allwinner_rtc_sun4i_regmap);
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arc->read = allwinner_rtc_sun4i_read;
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arc->write = allwinner_rtc_sun4i_write;
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}
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static void allwinner_rtc_sun6i_init(Object *obj)
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{
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AwRtcState *s = AW_RTC(obj);
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s->base_year = 1970;
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}
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static void allwinner_rtc_sun6i_class_init(ObjectClass *klass, void *data)
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{
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AwRtcClass *arc = AW_RTC_CLASS(klass);
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arc->regmap = allwinner_rtc_sun6i_regmap;
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arc->regmap_size = sizeof(allwinner_rtc_sun6i_regmap);
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arc->read = allwinner_rtc_sun6i_read;
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arc->write = allwinner_rtc_sun6i_write;
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}
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static void allwinner_rtc_sun7i_init(Object *obj)
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{
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AwRtcState *s = AW_RTC(obj);
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s->base_year = 1970;
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}
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static void allwinner_rtc_sun7i_class_init(ObjectClass *klass, void *data)
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{
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AwRtcClass *arc = AW_RTC_CLASS(klass);
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allwinner_rtc_sun4i_class_init(klass, arc);
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}
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static const TypeInfo allwinner_rtc_info = {
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.name = TYPE_AW_RTC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_init = allwinner_rtc_init,
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.instance_size = sizeof(AwRtcState),
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.class_init = allwinner_rtc_class_init,
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.class_size = sizeof(AwRtcClass),
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.abstract = true,
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};
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static const TypeInfo allwinner_rtc_sun4i_info = {
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.name = TYPE_AW_RTC_SUN4I,
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.parent = TYPE_AW_RTC,
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.class_init = allwinner_rtc_sun4i_class_init,
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.instance_init = allwinner_rtc_sun4i_init,
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};
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static const TypeInfo allwinner_rtc_sun6i_info = {
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.name = TYPE_AW_RTC_SUN6I,
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.parent = TYPE_AW_RTC,
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.class_init = allwinner_rtc_sun6i_class_init,
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.instance_init = allwinner_rtc_sun6i_init,
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};
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static const TypeInfo allwinner_rtc_sun7i_info = {
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.name = TYPE_AW_RTC_SUN7I,
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.parent = TYPE_AW_RTC,
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.class_init = allwinner_rtc_sun7i_class_init,
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.instance_init = allwinner_rtc_sun7i_init,
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};
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static void allwinner_rtc_register(void)
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{
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type_register_static(&allwinner_rtc_info);
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type_register_static(&allwinner_rtc_sun4i_info);
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type_register_static(&allwinner_rtc_sun6i_info);
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type_register_static(&allwinner_rtc_sun7i_info);
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}
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type_init(allwinner_rtc_register)
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