Frédéric Pétrot b3a5d1fbeb target/riscv: support for 128-bit M extension ... Mult are generated inline (using a cool trick pointed out by Richard), but for div and rem, given the complexity of the implementation of these instructions, we call helpers to produce their behavior. From an implementation standpoint, the helpers return the low part of the results, while the high part is temporarily stored in a dedicated field of cpu_env that is used to update the architectural register in the generation wrapper. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-15-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-01-08 15:46:10 +10:00
..
trans_privileged.c.inc	target/riscv: Remove exit_tb and lookup_and_goto_ptr	2021-10-15 16:39:14 -07:00
trans_rva.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvb.c.inc	target/riscv: support for 128-bit arithmetic instructions	2022-01-08 15:46:10 +10:00
trans_rvd.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvf.c.inc	target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions	2021-10-28 14:39:23 +10:00
trans_rvh.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvi.c.inc	target/riscv: support for 128-bit arithmetic instructions	2022-01-08 15:46:10 +10:00
trans_rvm.c.inc	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
trans_rvv.c.inc	target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing fp/int type-convert insns	2022-01-08 15:46:09 +10:00
trans_rvzfh.c.inc	target/riscv: zfh: implement zfhmin extension	2021-12-20 14:51:36 +10:00