fa947a667f
While we may have had some thought of allowing system-mode to return from this hook, we have no guests that require this. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
244 lines
6.5 KiB
C
244 lines
6.5 KiB
C
/*
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* Altera Nios II virtual CPU header
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*
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* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#ifndef NIOS2_CPU_H
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#define NIOS2_CPU_H
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#include "exec/cpu-defs.h"
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#include "hw/core/cpu.h"
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#include "qom/object.h"
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typedef struct CPUNios2State CPUNios2State;
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#if !defined(CONFIG_USER_ONLY)
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#include "mmu.h"
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#endif
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#define TYPE_NIOS2_CPU "nios2-cpu"
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OBJECT_DECLARE_TYPE(Nios2CPU, Nios2CPUClass,
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NIOS2_CPU)
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/**
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* Nios2CPUClass:
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* @parent_reset: The parent class' reset handler.
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*
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* A Nios2 CPU model.
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*/
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struct Nios2CPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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DeviceReset parent_reset;
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};
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#define TARGET_HAS_ICE 1
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/* Configuration options for Nios II */
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#define RESET_ADDRESS 0x00000000
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#define EXCEPTION_ADDRESS 0x00000004
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#define FAST_TLB_MISS_ADDRESS 0x00000008
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/* GP regs + CR regs + PC */
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#define NUM_CORE_REGS (32 + 32 + 1)
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/* General purpose register aliases */
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#define R_ZERO 0
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#define R_AT 1
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#define R_RET0 2
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#define R_RET1 3
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#define R_ARG0 4
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#define R_ARG1 5
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#define R_ARG2 6
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#define R_ARG3 7
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#define R_ET 24
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#define R_BT 25
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#define R_GP 26
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#define R_SP 27
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#define R_FP 28
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#define R_EA 29
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#define R_BA 30
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#define R_RA 31
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/* Control register aliases */
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#define CR_BASE 32
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#define CR_STATUS (CR_BASE + 0)
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#define CR_STATUS_PIE (1 << 0)
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#define CR_STATUS_U (1 << 1)
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#define CR_STATUS_EH (1 << 2)
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#define CR_STATUS_IH (1 << 3)
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#define CR_STATUS_IL (63 << 4)
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#define CR_STATUS_CRS (63 << 10)
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#define CR_STATUS_PRS (63 << 16)
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#define CR_STATUS_NMI (1 << 22)
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#define CR_STATUS_RSIE (1 << 23)
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#define CR_ESTATUS (CR_BASE + 1)
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#define CR_BSTATUS (CR_BASE + 2)
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#define CR_IENABLE (CR_BASE + 3)
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#define CR_IPENDING (CR_BASE + 4)
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#define CR_CPUID (CR_BASE + 5)
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#define CR_CTL6 (CR_BASE + 6)
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#define CR_EXCEPTION (CR_BASE + 7)
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#define CR_PTEADDR (CR_BASE + 8)
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#define CR_PTEADDR_PTBASE_SHIFT 22
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#define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT)
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#define CR_PTEADDR_VPN_SHIFT 2
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#define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT)
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#define CR_TLBACC (CR_BASE + 9)
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#define CR_TLBACC_IGN_SHIFT 25
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#define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT)
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#define CR_TLBACC_C (1 << 24)
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#define CR_TLBACC_R (1 << 23)
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#define CR_TLBACC_W (1 << 22)
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#define CR_TLBACC_X (1 << 21)
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#define CR_TLBACC_G (1 << 20)
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#define CR_TLBACC_PFN_MASK 0x000FFFFF
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#define CR_TLBMISC (CR_BASE + 10)
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#define CR_TLBMISC_WAY_SHIFT 20
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#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT)
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#define CR_TLBMISC_RD (1 << 19)
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#define CR_TLBMISC_WR (1 << 18)
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#define CR_TLBMISC_PID_SHIFT 4
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#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT)
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#define CR_TLBMISC_DBL (1 << 3)
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#define CR_TLBMISC_BAD (1 << 2)
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#define CR_TLBMISC_PERM (1 << 1)
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#define CR_TLBMISC_D (1 << 0)
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#define CR_ENCINJ (CR_BASE + 11)
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#define CR_BADADDR (CR_BASE + 12)
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#define CR_CONFIG (CR_BASE + 13)
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#define CR_MPUBASE (CR_BASE + 14)
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#define CR_MPUACC (CR_BASE + 15)
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/* Other registers */
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#define R_PC 64
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/* Exceptions */
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#define EXCP_BREAK 0x1000
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#define EXCP_RESET 0
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#define EXCP_PRESET 1
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#define EXCP_IRQ 2
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#define EXCP_TRAP 3
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#define EXCP_UNIMPL 4
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#define EXCP_ILLEGAL 5
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#define EXCP_UNALIGN 6
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#define EXCP_UNALIGND 7
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#define EXCP_DIV 8
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#define EXCP_SUPERA 9
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#define EXCP_SUPERI 10
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#define EXCP_SUPERD 11
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#define EXCP_TLBD 12
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#define EXCP_TLBX 13
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#define EXCP_TLBR 14
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#define EXCP_TLBW 15
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#define EXCP_MPUI 16
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#define EXCP_MPUD 17
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#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
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struct CPUNios2State {
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uint32_t regs[NUM_CORE_REGS];
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#if !defined(CONFIG_USER_ONLY)
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Nios2MMU mmu;
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uint32_t irq_pending;
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#endif
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};
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/**
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* Nios2CPU:
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* @env: #CPUNios2State
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*
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* A Nios2 CPU.
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*/
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struct Nios2CPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPUNios2State env;
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bool mmu_present;
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uint32_t pid_num_bits;
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uint32_t tlb_num_ways;
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uint32_t tlb_num_entries;
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/* Addresses that are hard-coded in the FPGA build settings */
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uint32_t reset_addr;
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uint32_t exception_addr;
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uint32_t fast_tlb_miss_addr;
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};
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void nios2_tcg_init(void);
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void nios2_cpu_do_interrupt(CPUState *cs);
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void dump_mmu(CPUNios2State *env);
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void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t retaddr) QEMU_NORETURN;
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void do_nios2_semihosting(CPUNios2State *env);
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#define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU
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#define cpu_gen_code cpu_nios2_gen_code
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#define CPU_SAVE_VERSION 1
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/* MMU modes definitions */
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#define MMU_SUPERVISOR_IDX 0
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#define MMU_USER_IDX 1
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static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
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{
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return (env->regs[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
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MMU_SUPERVISOR_IDX;
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}
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bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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static inline int cpu_interrupts_enabled(CPUNios2State *env)
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{
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return env->regs[CR_STATUS] & CR_STATUS_PIE;
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}
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typedef CPUNios2State CPUArchState;
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typedef Nios2CPU ArchCPU;
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#include "exec/cpu-all.h"
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static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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*pc = env->regs[R_PC];
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*cs_base = 0;
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*flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U));
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}
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#endif /* NIOS2_CPU_H */
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