qemu/tcg/riscv
Richard Henderson b86c6ba689 util/cpuinfo-riscv: Support host/cpuinfo.h for riscv
Move detection code out of tcg, similar to other hosts.

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-03 10:24:12 -07:00
..
tcg-target-con-set.h tcg/riscv: Support CTZ, CLZ from Zbb 2023-05-25 15:29:36 +00:00
tcg-target-con-str.h tcg/riscv: Support ANDN, ORN, XNOR from Zbb 2023-05-25 13:57:52 +00:00
tcg-target-reg-bits.h tcg: Split out tcg-target-reg-bits.h 2023-06-05 12:04:28 -07:00
tcg-target.c.inc util/cpuinfo-riscv: Support host/cpuinfo.h for riscv 2024-07-03 10:24:12 -07:00
tcg-target.h util/cpuinfo-riscv: Support host/cpuinfo.h for riscv 2024-07-03 10:24:12 -07:00