b33c17e12d
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3348 c046a42c-6fe2-441c-8c8c-71466251a162
1332 lines
37 KiB
C
1332 lines
37 KiB
C
/*
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* QEMU generic PowerPC hardware System Emulator
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#include "m48t59.h"
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//#define PPC_DEBUG_IRQ
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//#define PPC_DEBUG_TB
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extern FILE *logfile;
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extern int loglevel;
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static void ppc_set_irq (CPUState *env, int n_IRQ, int level)
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{
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if (level) {
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env->pending_interrupts |= 1 << n_IRQ;
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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} else {
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env->pending_interrupts &= ~(1 << n_IRQ);
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if (env->pending_interrupts == 0)
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n",
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__func__, env, n_IRQ, level,
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env->pending_interrupts, env->interrupt_request);
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}
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#endif
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}
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/* PowerPC 6xx / 7xx internal IRQ controller */
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static void ppc6xx_set_irq (void *opaque, int pin, int level)
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{
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CPUState *env = opaque;
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int cur_level;
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
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env, pin, level);
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}
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#endif
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cur_level = (env->irq_input_state >> pin) & 1;
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/* Don't generate spurious events */
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if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
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switch (pin) {
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case PPC6xx_INPUT_INT:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the external IRQ state to %d\n",
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__func__, level);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
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break;
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case PPC6xx_INPUT_SMI:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the SMI IRQ state to %d\n",
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__func__, level);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
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break;
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case PPC6xx_INPUT_MCP:
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/* Negative edge sensitive */
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/* XXX: TODO: actual reaction may depends on HID0 status
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* 603/604/740/750: check HID0[EMCP]
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*/
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if (cur_level == 1 && level == 0) {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: raise machine check state\n",
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__func__);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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}
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break;
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case PPC6xx_INPUT_CKSTP_IN:
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/* Level sensitive - active low */
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/* XXX: TODO: relay the signal to CKSTP_OUT pin */
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if (level) {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: stop the CPU\n", __func__);
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}
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#endif
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env->halted = 1;
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} else {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: restart the CPU\n", __func__);
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}
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#endif
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env->halted = 0;
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}
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break;
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case PPC6xx_INPUT_HRESET:
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/* Level sensitive - active low */
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if (level) {
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#if 0 // XXX: TOFIX
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: reset the CPU\n", __func__);
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}
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#endif
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cpu_reset(env);
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#endif
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}
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break;
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case PPC6xx_INPUT_SRESET:
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
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__func__, level);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
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break;
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default:
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/* Unknown pin - do nothing */
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
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}
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#endif
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return;
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}
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if (level)
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env->irq_input_state |= 1 << pin;
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else
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env->irq_input_state &= ~(1 << pin);
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}
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}
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void ppc6xx_irq_init (CPUState *env)
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{
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env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6);
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}
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#if defined(TARGET_PPC64)
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/* PowerPC 970 internal IRQ controller */
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static void ppc970_set_irq (void *opaque, int pin, int level)
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{
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CPUState *env = opaque;
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int cur_level;
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
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env, pin, level);
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}
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#endif
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cur_level = (env->irq_input_state >> pin) & 1;
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/* Don't generate spurious events */
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if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
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switch (pin) {
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case PPC970_INPUT_INT:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the external IRQ state to %d\n",
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__func__, level);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
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break;
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case PPC970_INPUT_THINT:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__,
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level);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
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break;
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case PPC970_INPUT_MCP:
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/* Negative edge sensitive */
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/* XXX: TODO: actual reaction may depends on HID0 status
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* 603/604/740/750: check HID0[EMCP]
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*/
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if (cur_level == 1 && level == 0) {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: raise machine check state\n",
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__func__);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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}
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break;
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case PPC970_INPUT_CKSTP:
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/* Level sensitive - active low */
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/* XXX: TODO: relay the signal to CKSTP_OUT pin */
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if (level) {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: stop the CPU\n", __func__);
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}
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#endif
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env->halted = 1;
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} else {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: restart the CPU\n", __func__);
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}
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#endif
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env->halted = 0;
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}
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break;
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case PPC970_INPUT_HRESET:
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/* Level sensitive - active low */
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if (level) {
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#if 0 // XXX: TOFIX
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: reset the CPU\n", __func__);
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}
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#endif
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cpu_reset(env);
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#endif
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}
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break;
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case PPC970_INPUT_SRESET:
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
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__func__, level);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
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break;
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case PPC970_INPUT_TBEN:
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the TBEN state to %d\n", __func__,
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level);
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}
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#endif
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/* XXX: TODO */
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break;
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default:
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/* Unknown pin - do nothing */
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
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}
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#endif
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return;
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}
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if (level)
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env->irq_input_state |= 1 << pin;
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else
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env->irq_input_state &= ~(1 << pin);
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}
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}
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void ppc970_irq_init (CPUState *env)
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{
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env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
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}
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#endif /* defined(TARGET_PPC64) */
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/* PowerPC 40x internal IRQ controller */
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static void ppc40x_set_irq (void *opaque, int pin, int level)
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{
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CPUState *env = opaque;
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int cur_level;
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
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env, pin, level);
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}
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#endif
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cur_level = (env->irq_input_state >> pin) & 1;
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/* Don't generate spurious events */
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if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
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switch (pin) {
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case PPC40x_INPUT_RESET_SYS:
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if (level) {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: reset the PowerPC system\n",
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__func__);
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}
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#endif
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ppc40x_system_reset(env);
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}
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break;
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case PPC40x_INPUT_RESET_CHIP:
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if (level) {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: reset the PowerPC chip\n", __func__);
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}
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#endif
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ppc40x_chip_reset(env);
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}
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break;
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case PPC40x_INPUT_RESET_CORE:
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/* XXX: TODO: update DBSR[MRR] */
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if (level) {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: reset the PowerPC core\n", __func__);
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}
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#endif
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ppc40x_core_reset(env);
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}
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break;
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case PPC40x_INPUT_CINT:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the critical IRQ state to %d\n",
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__func__, level);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
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break;
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case PPC40x_INPUT_INT:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the external IRQ state to %d\n",
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__func__, level);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
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break;
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case PPC40x_INPUT_HALT:
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/* Level sensitive - active low */
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if (level) {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: stop the CPU\n", __func__);
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}
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#endif
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env->halted = 1;
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} else {
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: restart the CPU\n", __func__);
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}
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#endif
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env->halted = 0;
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}
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break;
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case PPC40x_INPUT_DEBUG:
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/* Level sensitive - active high */
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: set the debug pin state to %d\n",
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__func__, level);
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}
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#endif
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ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
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break;
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default:
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/* Unknown pin - do nothing */
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#if defined(PPC_DEBUG_IRQ)
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if (loglevel & CPU_LOG_INT) {
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fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
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}
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#endif
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return;
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}
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if (level)
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env->irq_input_state |= 1 << pin;
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else
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env->irq_input_state &= ~(1 << pin);
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}
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}
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void ppc40x_irq_init (CPUState *env)
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{
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env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
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env, PPC40x_INPUT_NB);
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}
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/*****************************************************************************/
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/* PowerPC time base and decrementer emulation */
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struct ppc_tb_t {
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/* Time base management */
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int64_t tb_offset; /* Compensation */
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int64_t atb_offset; /* Compensation */
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uint32_t tb_freq; /* TB frequency */
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/* Decrementer management */
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uint64_t decr_next; /* Tick for next decr interrupt */
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struct QEMUTimer *decr_timer;
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#if defined(TARGET_PPC64H)
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/* Hypervisor decrementer management */
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uint64_t hdecr_next; /* Tick for next hdecr interrupt */
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struct QEMUTimer *hdecr_timer;
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uint64_t purr_load;
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uint64_t purr_start;
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#endif
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void *opaque;
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};
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static always_inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env,
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int64_t tb_offset)
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{
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/* TB time in tb periods */
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return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
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tb_env->tb_freq, ticks_per_sec);
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}
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uint32_t cpu_ppc_load_tbl (CPUState *env)
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{
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ppc_tb_t *tb_env = env->tb_env;
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uint64_t tb;
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tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
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#if defined(PPC_DEBUG_TB)
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if (loglevel != 0) {
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fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
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}
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#endif
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return tb & 0xFFFFFFFF;
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}
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static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env)
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{
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ppc_tb_t *tb_env = env->tb_env;
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uint64_t tb;
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tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
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#if defined(PPC_DEBUG_TB)
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if (loglevel != 0) {
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fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
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}
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#endif
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return tb >> 32;
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}
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uint32_t cpu_ppc_load_tbu (CPUState *env)
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{
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return _cpu_ppc_load_tbu(env);
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}
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static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env,
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int64_t *tb_offsetp,
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uint64_t value)
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{
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*tb_offsetp = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
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- qemu_get_clock(vm_clock);
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#ifdef PPC_DEBUG_TB
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if (loglevel != 0) {
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fprintf(logfile, "%s: tb=0x%016lx offset=%08lx\n", __func__, value,
|
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*tb_offsetp);
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}
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#endif
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}
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void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
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{
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ppc_tb_t *tb_env = env->tb_env;
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uint64_t tb;
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tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
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tb &= 0xFFFFFFFF00000000ULL;
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cpu_ppc_store_tb(tb_env, &tb_env->tb_offset, tb | (uint64_t)value);
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}
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static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value)
|
|
{
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
uint64_t tb;
|
|
|
|
tb = cpu_ppc_get_tb(tb_env, tb_env->tb_offset);
|
|
tb &= 0x00000000FFFFFFFFULL;
|
|
cpu_ppc_store_tb(tb_env, &tb_env->tb_offset,
|
|
((uint64_t)value << 32) | tb);
|
|
}
|
|
|
|
void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
|
|
{
|
|
_cpu_ppc_store_tbu(env, value);
|
|
}
|
|
|
|
uint32_t cpu_ppc_load_atbl (CPUState *env)
|
|
{
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
uint64_t tb;
|
|
|
|
tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
|
|
#if defined(PPC_DEBUG_TB)
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
|
|
}
|
|
#endif
|
|
|
|
return tb & 0xFFFFFFFF;
|
|
}
|
|
|
|
uint32_t cpu_ppc_load_atbu (CPUState *env)
|
|
{
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
uint64_t tb;
|
|
|
|
tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
|
|
#if defined(PPC_DEBUG_TB)
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
|
|
}
|
|
#endif
|
|
|
|
return tb >> 32;
|
|
}
|
|
|
|
void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
|
|
{
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
uint64_t tb;
|
|
|
|
tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
|
|
tb &= 0xFFFFFFFF00000000ULL;
|
|
cpu_ppc_store_tb(tb_env, &tb_env->atb_offset, tb | (uint64_t)value);
|
|
}
|
|
|
|
void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
|
|
{
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
uint64_t tb;
|
|
|
|
tb = cpu_ppc_get_tb(tb_env, tb_env->atb_offset);
|
|
tb &= 0x00000000FFFFFFFFULL;
|
|
cpu_ppc_store_tb(tb_env, &tb_env->atb_offset,
|
|
((uint64_t)value << 32) | tb);
|
|
}
|
|
|
|
static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env,
|
|
uint64_t *next)
|
|
{
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
uint32_t decr;
|
|
int64_t diff;
|
|
|
|
diff = tb_env->decr_next - qemu_get_clock(vm_clock);
|
|
if (diff >= 0)
|
|
decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
|
|
else
|
|
decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
|
|
#if defined(PPC_DEBUG_TB)
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s: 0x%08x\n", __func__, decr);
|
|
}
|
|
#endif
|
|
|
|
return decr;
|
|
}
|
|
|
|
uint32_t cpu_ppc_load_decr (CPUState *env)
|
|
{
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
|
|
return _cpu_ppc_load_decr(env, &tb_env->decr_next);
|
|
}
|
|
|
|
#if defined(TARGET_PPC64H)
|
|
uint32_t cpu_ppc_load_hdecr (CPUState *env)
|
|
{
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
|
|
return _cpu_ppc_load_decr(env, &tb_env->hdecr_next);
|
|
}
|
|
|
|
uint64_t cpu_ppc_load_purr (CPUState *env)
|
|
{
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
uint64_t diff;
|
|
|
|
diff = qemu_get_clock(vm_clock) - tb_env->purr_start;
|
|
|
|
return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
|
|
}
|
|
#endif /* defined(TARGET_PPC64H) */
|
|
|
|
/* When decrementer expires,
|
|
* all we need to do is generate or queue a CPU exception
|
|
*/
|
|
static always_inline void cpu_ppc_decr_excp (CPUState *env)
|
|
{
|
|
/* Raise it */
|
|
#ifdef PPC_DEBUG_TB
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "raise decrementer exception\n");
|
|
}
|
|
#endif
|
|
ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
|
|
}
|
|
|
|
static always_inline void cpu_ppc_hdecr_excp (CPUState *env)
|
|
{
|
|
/* Raise it */
|
|
#ifdef PPC_DEBUG_TB
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "raise decrementer exception\n");
|
|
}
|
|
#endif
|
|
ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
|
|
}
|
|
|
|
static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
|
|
struct QEMUTimer *timer,
|
|
void (*raise_excp)(CPUState *),
|
|
uint32_t decr, uint32_t value,
|
|
int is_excp)
|
|
{
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
uint64_t now, next;
|
|
|
|
#ifdef PPC_DEBUG_TB
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value);
|
|
}
|
|
#endif
|
|
now = qemu_get_clock(vm_clock);
|
|
next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
|
|
if (is_excp)
|
|
next += *nextp - now;
|
|
if (next == now)
|
|
next++;
|
|
*nextp = next;
|
|
/* Adjust timer */
|
|
qemu_mod_timer(timer, next);
|
|
/* If we set a negative value and the decrementer was positive,
|
|
* raise an exception.
|
|
*/
|
|
if ((value & 0x80000000) && !(decr & 0x80000000))
|
|
(*raise_excp)(env);
|
|
}
|
|
|
|
static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
|
|
uint32_t value, int is_excp)
|
|
{
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
|
|
__cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer,
|
|
&cpu_ppc_decr_excp, decr, value, is_excp);
|
|
}
|
|
|
|
void cpu_ppc_store_decr (CPUState *env, uint32_t value)
|
|
{
|
|
_cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
|
|
}
|
|
|
|
static void cpu_ppc_decr_cb (void *opaque)
|
|
{
|
|
_cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
|
|
}
|
|
|
|
#if defined(TARGET_PPC64H)
|
|
static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,
|
|
uint32_t value, int is_excp)
|
|
{
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
|
|
__cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,
|
|
&cpu_ppc_hdecr_excp, hdecr, value, is_excp);
|
|
}
|
|
|
|
void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
|
|
{
|
|
_cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
|
|
}
|
|
|
|
static void cpu_ppc_hdecr_cb (void *opaque)
|
|
{
|
|
_cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1);
|
|
}
|
|
|
|
void cpu_ppc_store_purr (CPUState *env, uint64_t value)
|
|
{
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
|
|
tb_env->purr_load = value;
|
|
tb_env->purr_start = qemu_get_clock(vm_clock);
|
|
}
|
|
#endif /* defined(TARGET_PPC64H) */
|
|
|
|
static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
|
|
{
|
|
CPUState *env = opaque;
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
|
|
tb_env->tb_freq = freq;
|
|
/* There is a bug in Linux 2.4 kernels:
|
|
* if a decrementer exception is pending when it enables msr_ee at startup,
|
|
* it's not ready to handle it...
|
|
*/
|
|
_cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
|
|
#if defined(TARGET_PPC64H)
|
|
_cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
|
|
cpu_ppc_store_purr(env, 0x0000000000000000ULL);
|
|
#endif /* defined(TARGET_PPC64H) */
|
|
}
|
|
|
|
/* Set up (once) timebase frequency (in Hz) */
|
|
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)
|
|
{
|
|
ppc_tb_t *tb_env;
|
|
|
|
tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
|
if (tb_env == NULL)
|
|
return NULL;
|
|
env->tb_env = tb_env;
|
|
/* Create new timer */
|
|
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
|
|
#if defined(TARGET_PPC64H)
|
|
tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);
|
|
#endif /* defined(TARGET_PPC64H) */
|
|
cpu_ppc_set_tb_clk(env, freq);
|
|
|
|
return &cpu_ppc_set_tb_clk;
|
|
}
|
|
|
|
/* Specific helpers for POWER & PowerPC 601 RTC */
|
|
clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
|
|
{
|
|
return cpu_ppc_tb_init(env, 7812500);
|
|
}
|
|
|
|
void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
|
|
{
|
|
_cpu_ppc_store_tbu(env, value);
|
|
}
|
|
|
|
uint32_t cpu_ppc601_load_rtcu (CPUState *env)
|
|
{
|
|
return _cpu_ppc_load_tbu(env);
|
|
}
|
|
|
|
void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
|
|
{
|
|
cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
|
|
}
|
|
|
|
uint32_t cpu_ppc601_load_rtcl (CPUState *env)
|
|
{
|
|
return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/* Embedded PowerPC timers */
|
|
|
|
/* PIT, FIT & WDT */
|
|
typedef struct ppcemb_timer_t ppcemb_timer_t;
|
|
struct ppcemb_timer_t {
|
|
uint64_t pit_reload; /* PIT auto-reload value */
|
|
uint64_t fit_next; /* Tick for next FIT interrupt */
|
|
struct QEMUTimer *fit_timer;
|
|
uint64_t wdt_next; /* Tick for next WDT interrupt */
|
|
struct QEMUTimer *wdt_timer;
|
|
};
|
|
|
|
/* Fixed interval timer */
|
|
static void cpu_4xx_fit_cb (void *opaque)
|
|
{
|
|
CPUState *env;
|
|
ppc_tb_t *tb_env;
|
|
ppcemb_timer_t *ppcemb_timer;
|
|
uint64_t now, next;
|
|
|
|
env = opaque;
|
|
tb_env = env->tb_env;
|
|
ppcemb_timer = tb_env->opaque;
|
|
now = qemu_get_clock(vm_clock);
|
|
switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
|
|
case 0:
|
|
next = 1 << 9;
|
|
break;
|
|
case 1:
|
|
next = 1 << 13;
|
|
break;
|
|
case 2:
|
|
next = 1 << 17;
|
|
break;
|
|
case 3:
|
|
next = 1 << 21;
|
|
break;
|
|
default:
|
|
/* Cannot occur, but makes gcc happy */
|
|
return;
|
|
}
|
|
next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
|
|
if (next == now)
|
|
next++;
|
|
qemu_mod_timer(ppcemb_timer->fit_timer, next);
|
|
env->spr[SPR_40x_TSR] |= 1 << 26;
|
|
if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
|
|
ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
|
|
#ifdef PPC_DEBUG_TB
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
|
|
(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
|
|
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* Programmable interval timer */
|
|
static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
|
|
{
|
|
ppcemb_timer_t *ppcemb_timer;
|
|
uint64_t now, next;
|
|
|
|
ppcemb_timer = tb_env->opaque;
|
|
if (ppcemb_timer->pit_reload <= 1 ||
|
|
!((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
|
|
(is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
|
|
/* Stop PIT */
|
|
#ifdef PPC_DEBUG_TB
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s: stop PIT\n", __func__);
|
|
}
|
|
#endif
|
|
qemu_del_timer(tb_env->decr_timer);
|
|
} else {
|
|
#ifdef PPC_DEBUG_TB
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s: start PIT 0x" REGX "\n",
|
|
__func__, ppcemb_timer->pit_reload);
|
|
}
|
|
#endif
|
|
now = qemu_get_clock(vm_clock);
|
|
next = now + muldiv64(ppcemb_timer->pit_reload,
|
|
ticks_per_sec, tb_env->tb_freq);
|
|
if (is_excp)
|
|
next += tb_env->decr_next - now;
|
|
if (next == now)
|
|
next++;
|
|
qemu_mod_timer(tb_env->decr_timer, next);
|
|
tb_env->decr_next = next;
|
|
}
|
|
}
|
|
|
|
static void cpu_4xx_pit_cb (void *opaque)
|
|
{
|
|
CPUState *env;
|
|
ppc_tb_t *tb_env;
|
|
ppcemb_timer_t *ppcemb_timer;
|
|
|
|
env = opaque;
|
|
tb_env = env->tb_env;
|
|
ppcemb_timer = tb_env->opaque;
|
|
env->spr[SPR_40x_TSR] |= 1 << 27;
|
|
if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
|
|
ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
|
|
start_stop_pit(env, tb_env, 1);
|
|
#ifdef PPC_DEBUG_TB
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
|
|
"%016" PRIx64 "\n", __func__,
|
|
(int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
|
|
(int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
|
|
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
|
|
ppcemb_timer->pit_reload);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* Watchdog timer */
|
|
static void cpu_4xx_wdt_cb (void *opaque)
|
|
{
|
|
CPUState *env;
|
|
ppc_tb_t *tb_env;
|
|
ppcemb_timer_t *ppcemb_timer;
|
|
uint64_t now, next;
|
|
|
|
env = opaque;
|
|
tb_env = env->tb_env;
|
|
ppcemb_timer = tb_env->opaque;
|
|
now = qemu_get_clock(vm_clock);
|
|
switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
|
|
case 0:
|
|
next = 1 << 17;
|
|
break;
|
|
case 1:
|
|
next = 1 << 21;
|
|
break;
|
|
case 2:
|
|
next = 1 << 25;
|
|
break;
|
|
case 3:
|
|
next = 1 << 29;
|
|
break;
|
|
default:
|
|
/* Cannot occur, but makes gcc happy */
|
|
return;
|
|
}
|
|
next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
|
|
if (next == now)
|
|
next++;
|
|
#ifdef PPC_DEBUG_TB
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
|
|
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
|
|
}
|
|
#endif
|
|
switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
|
|
case 0x0:
|
|
case 0x1:
|
|
qemu_mod_timer(ppcemb_timer->wdt_timer, next);
|
|
ppcemb_timer->wdt_next = next;
|
|
env->spr[SPR_40x_TSR] |= 1 << 31;
|
|
break;
|
|
case 0x2:
|
|
qemu_mod_timer(ppcemb_timer->wdt_timer, next);
|
|
ppcemb_timer->wdt_next = next;
|
|
env->spr[SPR_40x_TSR] |= 1 << 30;
|
|
if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)
|
|
ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
|
|
break;
|
|
case 0x3:
|
|
env->spr[SPR_40x_TSR] &= ~0x30000000;
|
|
env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
|
|
switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
|
|
case 0x0:
|
|
/* No reset */
|
|
break;
|
|
case 0x1: /* Core reset */
|
|
ppc40x_core_reset(env);
|
|
break;
|
|
case 0x2: /* Chip reset */
|
|
ppc40x_chip_reset(env);
|
|
break;
|
|
case 0x3: /* System reset */
|
|
ppc40x_system_reset(env);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void store_40x_pit (CPUState *env, target_ulong val)
|
|
{
|
|
ppc_tb_t *tb_env;
|
|
ppcemb_timer_t *ppcemb_timer;
|
|
|
|
tb_env = env->tb_env;
|
|
ppcemb_timer = tb_env->opaque;
|
|
#ifdef PPC_DEBUG_TB
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
|
|
}
|
|
#endif
|
|
ppcemb_timer->pit_reload = val;
|
|
start_stop_pit(env, tb_env, 0);
|
|
}
|
|
|
|
target_ulong load_40x_pit (CPUState *env)
|
|
{
|
|
return cpu_ppc_load_decr(env);
|
|
}
|
|
|
|
void store_booke_tsr (CPUState *env, target_ulong val)
|
|
{
|
|
#ifdef PPC_DEBUG_TB
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
|
|
}
|
|
#endif
|
|
env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
|
|
if (val & 0x80000000)
|
|
ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
|
|
}
|
|
|
|
void store_booke_tcr (CPUState *env, target_ulong val)
|
|
{
|
|
ppc_tb_t *tb_env;
|
|
|
|
tb_env = env->tb_env;
|
|
#ifdef PPC_DEBUG_TB
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s: val=" ADDRX "\n", __func__, val);
|
|
}
|
|
#endif
|
|
env->spr[SPR_40x_TCR] = val & 0xFFC00000;
|
|
start_stop_pit(env, tb_env, 1);
|
|
cpu_4xx_wdt_cb(env);
|
|
}
|
|
|
|
static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq)
|
|
{
|
|
CPUState *env = opaque;
|
|
ppc_tb_t *tb_env = env->tb_env;
|
|
|
|
#ifdef PPC_DEBUG_TB
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s set new frequency to %u\n", __func__, freq);
|
|
}
|
|
#endif
|
|
tb_env->tb_freq = freq;
|
|
/* XXX: we should also update all timers */
|
|
}
|
|
|
|
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
|
|
{
|
|
ppc_tb_t *tb_env;
|
|
ppcemb_timer_t *ppcemb_timer;
|
|
|
|
tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
|
if (tb_env == NULL) {
|
|
return NULL;
|
|
}
|
|
env->tb_env = tb_env;
|
|
ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
|
|
tb_env->tb_freq = freq;
|
|
tb_env->opaque = ppcemb_timer;
|
|
#ifdef PPC_DEBUG_TB
|
|
if (loglevel != 0) {
|
|
fprintf(logfile, "%s %p %p %p\n", __func__, tb_env, ppcemb_timer,
|
|
&ppc_emb_set_tb_clk);
|
|
}
|
|
#endif
|
|
if (ppcemb_timer != NULL) {
|
|
/* We use decr timer for PIT */
|
|
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);
|
|
ppcemb_timer->fit_timer =
|
|
qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env);
|
|
ppcemb_timer->wdt_timer =
|
|
qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env);
|
|
}
|
|
|
|
return &ppc_emb_set_tb_clk;
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/* Embedded PowerPC Device Control Registers */
|
|
typedef struct ppc_dcrn_t ppc_dcrn_t;
|
|
struct ppc_dcrn_t {
|
|
dcr_read_cb dcr_read;
|
|
dcr_write_cb dcr_write;
|
|
void *opaque;
|
|
};
|
|
|
|
/* XXX: on 460, DCR addresses are 32 bits wide,
|
|
* using DCRIPR to get the 22 upper bits of the DCR address
|
|
*/
|
|
#define DCRN_NB 1024
|
|
struct ppc_dcr_t {
|
|
ppc_dcrn_t dcrn[DCRN_NB];
|
|
int (*read_error)(int dcrn);
|
|
int (*write_error)(int dcrn);
|
|
};
|
|
|
|
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
|
|
{
|
|
ppc_dcrn_t *dcr;
|
|
|
|
if (dcrn < 0 || dcrn >= DCRN_NB)
|
|
goto error;
|
|
dcr = &dcr_env->dcrn[dcrn];
|
|
if (dcr->dcr_read == NULL)
|
|
goto error;
|
|
*valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
|
|
|
|
return 0;
|
|
|
|
error:
|
|
if (dcr_env->read_error != NULL)
|
|
return (*dcr_env->read_error)(dcrn);
|
|
|
|
return -1;
|
|
}
|
|
|
|
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
|
|
{
|
|
ppc_dcrn_t *dcr;
|
|
|
|
if (dcrn < 0 || dcrn >= DCRN_NB)
|
|
goto error;
|
|
dcr = &dcr_env->dcrn[dcrn];
|
|
if (dcr->dcr_write == NULL)
|
|
goto error;
|
|
(*dcr->dcr_write)(dcr->opaque, dcrn, val);
|
|
|
|
return 0;
|
|
|
|
error:
|
|
if (dcr_env->write_error != NULL)
|
|
return (*dcr_env->write_error)(dcrn);
|
|
|
|
return -1;
|
|
}
|
|
|
|
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
|
|
dcr_read_cb dcr_read, dcr_write_cb dcr_write)
|
|
{
|
|
ppc_dcr_t *dcr_env;
|
|
ppc_dcrn_t *dcr;
|
|
|
|
dcr_env = env->dcr_env;
|
|
if (dcr_env == NULL)
|
|
return -1;
|
|
if (dcrn < 0 || dcrn >= DCRN_NB)
|
|
return -1;
|
|
dcr = &dcr_env->dcrn[dcrn];
|
|
if (dcr->opaque != NULL ||
|
|
dcr->dcr_read != NULL ||
|
|
dcr->dcr_write != NULL)
|
|
return -1;
|
|
dcr->opaque = opaque;
|
|
dcr->dcr_read = dcr_read;
|
|
dcr->dcr_write = dcr_write;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
|
|
int (*write_error)(int dcrn))
|
|
{
|
|
ppc_dcr_t *dcr_env;
|
|
|
|
dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
|
|
if (dcr_env == NULL)
|
|
return -1;
|
|
dcr_env->read_error = read_error;
|
|
dcr_env->write_error = write_error;
|
|
env->dcr_env = dcr_env;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if 0
|
|
/*****************************************************************************/
|
|
/* Handle system reset (for now, just stop emulation) */
|
|
void cpu_ppc_reset (CPUState *env)
|
|
{
|
|
printf("Reset asked... Stop emulation\n");
|
|
abort();
|
|
}
|
|
#endif
|
|
|
|
/*****************************************************************************/
|
|
/* Debug port */
|
|
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
addr &= 0xF;
|
|
switch (addr) {
|
|
case 0:
|
|
printf("%c", val);
|
|
break;
|
|
case 1:
|
|
printf("\n");
|
|
fflush(stdout);
|
|
break;
|
|
case 2:
|
|
printf("Set loglevel to %04x\n", val);
|
|
cpu_set_log(val | 0x100);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/* NVRAM helpers */
|
|
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
|
|
{
|
|
m48t59_write(nvram, addr, value);
|
|
}
|
|
|
|
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
|
|
{
|
|
return m48t59_read(nvram, addr);
|
|
}
|
|
|
|
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
|
|
{
|
|
m48t59_write(nvram, addr, value >> 8);
|
|
m48t59_write(nvram, addr + 1, value & 0xFF);
|
|
}
|
|
|
|
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
|
|
{
|
|
uint16_t tmp;
|
|
|
|
tmp = m48t59_read(nvram, addr) << 8;
|
|
tmp |= m48t59_read(nvram, addr + 1);
|
|
return tmp;
|
|
}
|
|
|
|
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
|
|
{
|
|
m48t59_write(nvram, addr, value >> 24);
|
|
m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
|
|
m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
|
|
m48t59_write(nvram, addr + 3, value & 0xFF);
|
|
}
|
|
|
|
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
|
|
{
|
|
uint32_t tmp;
|
|
|
|
tmp = m48t59_read(nvram, addr) << 24;
|
|
tmp |= m48t59_read(nvram, addr + 1) << 16;
|
|
tmp |= m48t59_read(nvram, addr + 2) << 8;
|
|
tmp |= m48t59_read(nvram, addr + 3);
|
|
|
|
return tmp;
|
|
}
|
|
|
|
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
|
|
const unsigned char *str, uint32_t max)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < max && str[i] != '\0'; i++) {
|
|
m48t59_write(nvram, addr + i, str[i]);
|
|
}
|
|
m48t59_write(nvram, addr + max - 1, '\0');
|
|
}
|
|
|
|
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
|
|
{
|
|
int i;
|
|
|
|
memset(dst, 0, max);
|
|
for (i = 0; i < max; i++) {
|
|
dst[i] = NVRAM_get_byte(nvram, addr + i);
|
|
if (dst[i] == '\0')
|
|
break;
|
|
}
|
|
|
|
return i;
|
|
}
|
|
|
|
static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
|
|
{
|
|
uint16_t tmp;
|
|
uint16_t pd, pd1, pd2;
|
|
|
|
tmp = prev >> 8;
|
|
pd = prev ^ value;
|
|
pd1 = pd & 0x000F;
|
|
pd2 = ((pd >> 4) & 0x000F) ^ pd1;
|
|
tmp ^= (pd1 << 3) | (pd1 << 8);
|
|
tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
|
|
|
|
return tmp;
|
|
}
|
|
|
|
uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
|
|
{
|
|
uint32_t i;
|
|
uint16_t crc = 0xFFFF;
|
|
int odd;
|
|
|
|
odd = count & 1;
|
|
count &= ~1;
|
|
for (i = 0; i != count; i++) {
|
|
crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
|
|
}
|
|
if (odd) {
|
|
crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
|
}
|
|
|
|
return crc;
|
|
}
|
|
|
|
#define CMDLINE_ADDR 0x017ff000
|
|
|
|
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
|
|
const unsigned char *arch,
|
|
uint32_t RAM_size, int boot_device,
|
|
uint32_t kernel_image, uint32_t kernel_size,
|
|
const char *cmdline,
|
|
uint32_t initrd_image, uint32_t initrd_size,
|
|
uint32_t NVRAM_image,
|
|
int width, int height, int depth)
|
|
{
|
|
uint16_t crc;
|
|
|
|
/* Set parameters for Open Hack'Ware BIOS */
|
|
NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
|
|
NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
|
|
NVRAM_set_word(nvram, 0x14, NVRAM_size);
|
|
NVRAM_set_string(nvram, 0x20, arch, 16);
|
|
NVRAM_set_lword(nvram, 0x30, RAM_size);
|
|
NVRAM_set_byte(nvram, 0x34, boot_device);
|
|
NVRAM_set_lword(nvram, 0x38, kernel_image);
|
|
NVRAM_set_lword(nvram, 0x3C, kernel_size);
|
|
if (cmdline) {
|
|
/* XXX: put the cmdline in NVRAM too ? */
|
|
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
|
|
NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
|
NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
|
|
} else {
|
|
NVRAM_set_lword(nvram, 0x40, 0);
|
|
NVRAM_set_lword(nvram, 0x44, 0);
|
|
}
|
|
NVRAM_set_lword(nvram, 0x48, initrd_image);
|
|
NVRAM_set_lword(nvram, 0x4C, initrd_size);
|
|
NVRAM_set_lword(nvram, 0x50, NVRAM_image);
|
|
|
|
NVRAM_set_word(nvram, 0x54, width);
|
|
NVRAM_set_word(nvram, 0x56, height);
|
|
NVRAM_set_word(nvram, 0x58, depth);
|
|
crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
|
|
NVRAM_set_word(nvram, 0xFC, crc);
|
|
|
|
return 0;
|
|
}
|