b2e2247716
For the time being, the XIVE reset handler updates the OS CAM line of the vCPU as it is done under a real hypervisor when a vCPU is scheduled to run on a HW thread. This will let the XIVE presenter engine find a match among the NVTs dispatched on the HW threads. This handler will become even more useful when we introduce the machine supporting both interrupt modes, XIVE and XICS. In this machine, the interrupt mode is chosen by the CAS negotiation process and activated after a reset. Signed-off-by: Cédric Le Goater <clg@kaod.org> [dwg: Fix style nits] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
/*
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* QEMU PowerPC sPAPR XIVE interrupt controller model
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*
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* Copyright (c) 2017-2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef PPC_SPAPR_XIVE_H
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#define PPC_SPAPR_XIVE_H
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#include "hw/ppc/xive.h"
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#define TYPE_SPAPR_XIVE "spapr-xive"
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#define SPAPR_XIVE(obj) OBJECT_CHECK(sPAPRXive, (obj), TYPE_SPAPR_XIVE)
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typedef struct sPAPRXive {
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XiveRouter parent;
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/* Internal interrupt source for IPIs and virtual devices */
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XiveSource source;
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hwaddr vc_base;
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/* END ESB MMIOs */
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XiveENDSource end_source;
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hwaddr end_base;
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/* Routing table */
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XiveEAS *eat;
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uint32_t nr_irqs;
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XiveEND *endt;
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uint32_t nr_ends;
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/* TIMA mapping address */
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hwaddr tm_base;
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MemoryRegion tm_mmio;
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} sPAPRXive;
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bool spapr_xive_irq_claim(sPAPRXive *xive, uint32_t lisn, bool lsi);
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bool spapr_xive_irq_free(sPAPRXive *xive, uint32_t lisn);
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void spapr_xive_pic_print_info(sPAPRXive *xive, Monitor *mon);
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qemu_irq spapr_xive_qirq(sPAPRXive *xive, uint32_t lisn);
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typedef struct sPAPRMachineState sPAPRMachineState;
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void spapr_xive_hcall_init(sPAPRMachineState *spapr);
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void spapr_dt_xive(sPAPRMachineState *spapr, uint32_t nr_servers, void *fdt,
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uint32_t phandle);
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void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx);
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#endif /* PPC_SPAPR_XIVE_H */
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