qemu/target
Peter Maydell 808ebd66e4 First RISC-V Patch Set for the 3.1 Soft Freeze
This pull request contains a handful of patches that have been floating
 around various trees for a while but haven't made it upstream.  These
 patches all appear quite safe.  They're all somewhat independent from
 each other:
 
 * One refactors our IRQ management function to allow multiple interrupts
   to be raised an once.  This patch has no functional difference.
 * Cleaning up the op_helper/cpu_helper split.  This patch has no
   functional difference.
 * Updates to various constants to keep them in sync with the latest ISA
   specification and to remove some non-standard bits that snuck in.
 * A fix for a memory leak in the PLIC driver.
 * A fix to our device tree handling to avoid provinging a NULL string.
 
 I've given this my standard test: building the port, booting a Fedora
 root filesytem on the latest Linux tag, and then shutting down that
 image.  Essentially I'm just following the QEMU RISC-V wiki page's
 instructions.  Everything looks fine here.
 
 We have a lot more outstanding patches so I'll definately be submitting
 another PR for the soft freeze.
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Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf0' into staging

First RISC-V Patch Set for the 3.1 Soft Freeze

This pull request contains a handful of patches that have been floating
around various trees for a while but haven't made it upstream.  These
patches all appear quite safe.  They're all somewhat independent from
each other:

* One refactors our IRQ management function to allow multiple interrupts
  to be raised an once.  This patch has no functional difference.
* Cleaning up the op_helper/cpu_helper split.  This patch has no
  functional difference.
* Updates to various constants to keep them in sync with the latest ISA
  specification and to remove some non-standard bits that snuck in.
* A fix for a memory leak in the PLIC driver.
* A fix to our device tree handling to avoid provinging a NULL string.

I've given this my standard test: building the port, booting a Fedora
root filesytem on the latest Linux tag, and then shutting down that
image.  Essentially I'm just following the QEMU RISC-V wiki page's
instructions.  Everything looks fine here.

We have a lot more outstanding patches so I'll definately be submitting
another PR for the soft freeze.

# gpg: Signature made Wed 17 Oct 2018 21:17:52 BST
# gpg:                using RSA key EF4CA1502CCBAB41
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>"
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/riscv/tags/riscv-for-master-3.1-sf0:
  RISC-V: Don't add NULL bootargs to device-tree
  RISC-V: Add missing free for plic_hart_config
  RISC-V: Update CSR and interrupt definitions
  RISC-V: Move non-ops from op_helper to cpu_helper
  RISC-V: Allow setting and clearing multiple irqs

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-10-25 17:41:03 +01:00
..
alpha target/alpha: remove tlb_flush from alpha_cpu_initfn 2018-10-18 18:58:10 -07:00
arm target/arm: Only flush tlb if ASID changes 2018-10-24 07:51:37 +01:00
cris target/cris/translate: Get rid of qemu_log_separate() 2018-10-16 17:57:23 +02:00
hppa target/hppa: Raise exception 26 on emulated hardware 2018-10-16 15:32:22 -07:00
i386 Error reporting patches for 2018-10-22 2018-10-23 17:20:23 +01:00
lm32 tcg-next queue 2018-06-04 11:28:31 +01:00
m68k target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn 2018-06-11 12:43:42 +02:00
microblaze target-microblaze: Rework NOP/zero instruction handling 2018-06-15 09:05:00 +02:00
mips target/mips: Fix decoding of ALIGN and DALIGN instructions 2018-10-24 15:20:32 +02:00
moxie tcg-next queue 2018-06-04 11:28:31 +01:00
nios2 tcg-next queue 2018-06-04 11:28:31 +01:00
openrisc target/openrisc: Fix writes to interrupt mask register 2018-07-03 22:40:33 +09:00
ppc Error reporting patches for 2018-10-22 2018-10-23 17:20:23 +01:00
riscv RISC-V: Update CSR and interrupt definitions 2018-10-17 13:02:19 -07:00
s390x target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate 2018-10-18 19:46:53 -07:00
sh4 sh4: fix use_icount with linux-user 2018-08-20 00:11:06 +02:00
sparc SPARC64: add icount support 2018-06-17 11:13:06 +01:00
tilegx tcg-next queue 2018-06-04 11:28:31 +01:00
tricore tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
unicore32 target/unicore32: remove tlb_flush from uc32_init_fn 2018-10-18 18:58:10 -07:00
xtensa target/xtensa: extract gen_check_interrupts call 2018-10-01 11:08:36 -07:00