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qemu/target/riscv
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Philippe Mathieu-Daudé b254c342cf accel/tcg: Access tcg_cflags with getter / setter 
Access the CPUState::tcg_cflags via tcg_cflags_has() and
tcg_cflags_set() helpers.

Mechanical change using the following Coccinelle spatch script:

  @@
  expression cpu;
  expression flags;
  @@
  -     cpu->tcg_cflags & flags
  +     tcg_cflags_has(cpu, flags)

  @@
  expression cpu;
  expression flags;
  @@
  -     (tcg_cflags_has(cpu, flags))
  +     tcg_cflags_has(cpu, flags)

  @@
  expression cpu;
  expression flags;
  @@
  -     cpu->tcg_cflags |= flags;
  +     tcg_cflags_set(cpu, flags);

Then manually moving the declarations, and adding both
tcg_cflags_has() and tcg_cflags_set() definitions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240427155714.53669-15-philmd@linaro.org>
2024-05-06 11:21:05 +02:00
..
insn_trans
target/riscv: enable 'vstart_eq_zero' in the end of insns
2024-03-22 15:24:37 +10:00
kvm
target/riscv/kvm: remove sneaky strerrorname_np() instance
2024-04-29 15:26:56 +03:00
tcg
accel/tcg: Access tcg_cflags with getter / setter
2024-05-06 11:21:05 +02:00
arch_dump.c
…
bitmanip_helper.c
…
common-semi-target.h
…
cpu_bits.h
target/riscv: FCSR doesn't contain vxrm and vxsat
2024-02-09 20:43:14 +10:00
cpu_cfg.h
target/riscv: do not enable all named features by default
2024-03-22 15:10:45 +10:00
cpu_helper.c
exec/cpu: Extract page-protection definitions to page-protection.h
2024-05-06 11:17:15 +02:00
cpu_user.h
…
cpu_vendorid.h
…
cpu-param.h
target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'
2024-04-26 15:31:37 +02:00
cpu-qom.h
target/riscv: add rv32i, rv32e and rv64e CPUs
2024-02-09 20:49:41 +10:00
cpu.c
hw, target: Add ResetType argument to hold and exit phase methods
2024-04-25 10:21:06 +01:00
cpu.h
target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'
2024-04-26 15:31:37 +02:00
crypto_helper.c
…
csr.c
target/riscv: UPDATE xATP write CSR
2024-03-08 16:38:09 +10:00
debug.c
target/riscv: Implement optional CSR mcontext of debug Sdtrig extension
2024-02-09 20:40:32 +10:00
debug.h
exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header
2024-04-26 17:03:05 +02:00
fpu_helper.c
…
gdbstub.c
gdbstub: Add members to identify registers to GDBFeature
2024-02-28 09:10:11 +00:00
helper.h
…
insn16.decode
…
insn32.decode
…
instmap.h
…
internals.h
…
Kconfig
kconfig: use "select" to enable semihosting
2024-02-09 17:52:30 +00:00
m128_helper.c
…
machine.c
target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit
2024-03-08 20:48:03 +10:00
meson.build
…
monitor.c
…
op_helper.c
…
pmp.c
exec/cpu: Extract page-protection definitions to page-protection.h
2024-05-06 11:17:15 +02:00
pmp.h
…
pmu.c
…
pmu.h
target/riscv: Add missing include guard in pmu.h
2024-03-08 16:39:32 +10:00
riscv-qmp-cmds.c
target: Improve error reporting for CpuModelInfo member @props
2024-03-12 14:03:00 +01:00
sbi_ecall_interface.h
…
time_helper.c
…
time_helper.h
…
trace-events
…
trace.h
…
translate.c
target/riscv: Use insn_start from DisasContextBase
2024-04-09 07:45:09 -10:00
vcrypto_helper.c
target/riscv/vector_helpers: do early exit when vstart >= vl
2024-03-22 15:20:02 +10:00
vector_helper.c
exec/cpu: Extract page-protection definitions to page-protection.h
2024-05-06 11:17:15 +02:00
vector_internals.c
target/riscv/vector_helpers: do early exit when vstart >= vl
2024-03-22 15:20:02 +10:00
vector_internals.h
target/riscv/vector_helpers: do early exit when vstart >= vl
2024-03-22 15:20:02 +10:00
xthead.decode
…
XVentanaCondOps.decode
…
zce_helper.c
…