f4c636b0c2
Convert the TYPE_CXL_ROOT_PORT and TYPE_PNV_PHB_ROOT_PORT classes to 3-phase reset, so they don't need to use the deprecated device_class_set_parent_reset() function any more. We have to do both in the same commit, because they keep the parent_reset field in their common parent class's class struct. Note that pnv_phb_root_port_class_init() was pointlessly setting dc->reset twice, once by calling device_class_set_parent_reset() and once directly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221125115240.3005559-5-peter.maydell@linaro.org
97 lines
2.6 KiB
C
97 lines
2.6 KiB
C
/*
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* pcie_port.h
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*
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef QEMU_PCIE_PORT_H
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#define QEMU_PCIE_PORT_H
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "qom/object.h"
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#define TYPE_PCIE_PORT "pcie-port"
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OBJECT_DECLARE_SIMPLE_TYPE(PCIEPort, PCIE_PORT)
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struct PCIEPort {
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/*< private >*/
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PCIBridge parent_obj;
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/*< public >*/
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/* pci express switch port */
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uint8_t port;
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};
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void pcie_port_init_reg(PCIDevice *d);
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PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn);
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#define TYPE_PCIE_SLOT "pcie-slot"
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OBJECT_DECLARE_SIMPLE_TYPE(PCIESlot, PCIE_SLOT)
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struct PCIESlot {
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/*< private >*/
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PCIEPort parent_obj;
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/*< public >*/
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/* pci express switch port with slot */
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uint8_t chassis;
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uint16_t slot;
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PCIExpLinkSpeed speed;
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PCIExpLinkWidth width;
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/* Disable ACS (really for a pcie_root_port) */
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bool disable_acs;
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/* Indicates whether any type of hot-plug is allowed on the slot */
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bool hotplug;
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bool native_hotplug;
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QLIST_ENTRY(PCIESlot) next;
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};
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void pcie_chassis_create(uint8_t chassis_number);
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PCIESlot *pcie_chassis_find_slot(uint8_t chassis, uint16_t slot);
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int pcie_chassis_add_slot(struct PCIESlot *slot);
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void pcie_chassis_del_slot(PCIESlot *s);
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#define TYPE_PCIE_ROOT_PORT "pcie-root-port-base"
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typedef struct PCIERootPortClass PCIERootPortClass;
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DECLARE_CLASS_CHECKERS(PCIERootPortClass, PCIE_ROOT_PORT,
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TYPE_PCIE_ROOT_PORT)
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struct PCIERootPortClass {
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PCIDeviceClass parent_class;
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DeviceRealize parent_realize;
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ResettablePhases parent_phases;
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uint8_t (*aer_vector)(const PCIDevice *dev);
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int (*interrupts_init)(PCIDevice *dev, Error **errp);
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void (*interrupts_uninit)(PCIDevice *dev);
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int exp_offset;
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int aer_offset;
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int ssvid_offset;
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int acs_offset; /* If nonzero, optional ACS capability offset */
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int ssid;
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};
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#endif /* QEMU_PCIE_PORT_H */
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