d0a9bb5ecb
Disconnect the layout of ArchCPU from TCG compilation. Pass the relative offset of 'env' and 'neg.tlb.f' as a parameter. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
57 lines
1.8 KiB
C
57 lines
1.8 KiB
C
/*
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* Common definitions for the softmmu tlb
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXEC_TLB_COMMON_H
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#define EXEC_TLB_COMMON_H 1
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#define CPU_TLB_ENTRY_BITS 5
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/* Minimalized TLB entry for use by TCG fast path. */
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typedef union CPUTLBEntry {
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struct {
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uint64_t addr_read;
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uint64_t addr_write;
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uint64_t addr_code;
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/*
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* Addend to virtual address to get host address. IO accesses
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* use the corresponding iotlb value.
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*/
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uintptr_t addend;
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};
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/*
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* Padding to get a power of two size, as well as index
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* access to addr_{read,write,code}.
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*/
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uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)];
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} CPUTLBEntry;
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QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
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/*
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* Data elements that are per MMU mode, accessed by the fast path.
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* The structure is aligned to aid loading the pair with one insn.
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*/
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typedef struct CPUTLBDescFast {
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/* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */
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uintptr_t mask;
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/* The array of tlb entries itself. */
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CPUTLBEntry *table;
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} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *));
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#endif /* EXEC_TLB_COMMON_H */
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