qemu/target
Peter Maydell 5cad8ca516 x86 queue, 2018-01-17
Highlight: new CPU models that expose CPU features that guests
 can use to mitigate CVE-2017-5715 (Spectre variant #2).
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJaX/+jAAoJECgHk2+YTcWmlzIP/i0oKKTtMccOozXQ8XbxfGs/
 Ek+k1joJSBRixUEB+hHHLraRmtw0b94R6uWXRF1KK9CPD06annHdr4tOAsryrQmp
 /lJfs7weGKi8o4Jz/YJW83NzNdNie0XloiS3+JGfu8fRh2EJDW3lv0j2CT3ytRlf
 rbal/j2E8lsmSsdL1lGbwb3E3DWDWIesWOGQMd3tu3WiMBMSgDqZa8RZo7hNiRsE
 7Vdj2yAWuj3vKRLSipIsSSOimr2P1hZsCMP2CI43BIvl6gW1S5ymExEppLNxruH6
 mqjAC96It3kqEZHVMPJg4evhwZitNxgqGtgrEbVfeZj+DTO/ZP6X6pcqtLdPA553
 dMrspDkYgU/OvE1ZQSMEXUm2IDt6fmpRiC4LvkWjMkvOOADIIBzL6LTzBd4k6fZ2
 hxQi+nc/IrIkQpq3f51YRVxwOs8otTBJzyqokxRvB3tOhg/I+NMxCvz5dyRjj5sN
 33eVdIuyndHiPTyvvv8eCjFeQG+wFFptPXMUhUEvJvQobJ/ZW76E+On8Kz3aYEF8
 lz++g3HvN7b7YPx3fqAvRfX/nZtDt04MDXvvnccXRt55Cn8tblQ92y84Wjc84SNZ
 lkgKhl4uOg6k7A1TblIhrk93eew/hSqaW8R8+y6qTUMkS6teAFsMrT0BSKETi1do
 GWTTbgH/3OECAQYFopBz
 =GtpX
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging

x86 queue, 2018-01-17

Highlight: new CPU models that expose CPU features that guests
can use to mitigate CVE-2017-5715 (Spectre variant #2).

# gpg: Signature made Thu 18 Jan 2018 02:00:03 GMT
# gpg:                using RSA key 0x2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-pull-request:
  i386: Add EPYC-IBPB CPU model
  i386: Add new -IBRS versions of Intel CPU models
  i386: Add FEAT_8000_0008_EBX CPUID feature word
  i386: Add spec-ctrl CPUID bit
  i386: Add support for SPEC_CTRL MSR
  i386: Change X86CPUDefinition::model_id to const char*
  target/i386: add clflushopt to "Skylake-Server" cpu model
  pc: add 2.12 machine types

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-18 12:59:24 +00:00
..
alpha tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
arm * QemuMutex tracing improvements (Alex) 2018-01-16 15:45:15 +00:00
cris tcg: Dynamically allocate TCGOps 2017-12-29 12:43:39 -08:00
hppa tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
i386 i386: Add EPYC-IBPB CPU model 2018-01-17 23:54:39 -02:00
lm32 tcg: Dynamically allocate TCGOps 2017-12-29 12:43:39 -08:00
m68k -----BEGIN PGP SIGNATURE----- 2018-01-08 21:39:44 +00:00
microblaze tcg: Dynamically allocate TCGOps 2017-12-29 12:43:39 -08:00
mips mips: Tweak location of ';' in macros 2018-01-16 14:54:51 +01:00
moxie target/moxie: Fix tlb_fill 2017-12-27 17:20:44 -08:00
nios2 tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
openrisc target/*helper: don't check retaddr before calling cpu_restore_state 2017-12-27 17:20:44 -08:00
ppc target-ppc: Fix booke206 tlbwe TLB instruction 2018-01-17 09:35:24 +11:00
s390x maint: Fix macros with broken 'do/while(0); ' usage 2018-01-16 14:54:52 +01:00
sh4 tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
sparc target/sparc: remove MemoryRegionSection check code from sparc_cpu_get_phys_page_debug() 2018-01-09 21:31:31 +00:00
tilegx tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
tricore target/*helper: don't check retaddr before calling cpu_restore_state 2017-12-27 17:20:44 -08:00
unicore32 tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* 2017-12-29 12:43:39 -08:00
xtensa target/xtensa: Remove duplicate typedef of DisasContext 2018-01-12 14:36:41 +00:00