01bc435b44
MIPS Release 6 provides multi-threading features which replace pre-R6 MT Module. CP0.Config3.MT is always 0 in R6, instead there is new CP0.Config5.VP (Virtual Processor) bit which indicates presence of multi-threading support which includes CP0.GlobalNumber register and DVP/EVP instructions. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> |
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| .. | ||
| libvixl | ||
| alpha.c | ||
| arm-a64.cc | ||
| arm.c | ||
| cris.c | ||
| hppa.c | ||
| i386.c | ||
| ia64.c | ||
| lm32.c | ||
| m68k.c | ||
| Makefile.objs | ||
| microblaze.c | ||
| mips.c | ||
| moxie.c | ||
| ppc.c | ||
| s390.c | ||
| sh4.c | ||
| sparc.c | ||
| tci.c | ||