b0fe242751
Implement the AArch64 memory attribute registers. Since QEMU doesn't model caches it does not need to care about memory attributes at all, and we can simply make these read-as-written. We did not previously implement the AArch32 versions of the MAIR registers, which went unnoticed because of the overbroad TLB_LOCKDOWN reginfo definition; provide them now to keep the 64<->32 register relationship clear. We already provided AMAIR registers for 32 bit as simple RAZ/WI; extend that to provide a 64 bit RAZ/WI AMAIR_EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> |
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| .. | ||
| arm-semi.c | ||
| cpu64.c | ||
| cpu-qom.h | ||
| cpu.c | ||
| cpu.h | ||
| crypto_helper.c | ||
| gdbstub64.c | ||
| gdbstub.c | ||
| helper-a64.c | ||
| helper-a64.h | ||
| helper.c | ||
| helper.h | ||
| iwmmxt_helper.c | ||
| kvm32.c | ||
| kvm64.c | ||
| kvm_arm.h | ||
| kvm-consts.h | ||
| kvm-stub.c | ||
| kvm.c | ||
| machine.c | ||
| Makefile.objs | ||
| neon_helper.c | ||
| op_addsub.h | ||
| op_helper.c | ||
| translate-a64.c | ||
| translate.c | ||
| translate.h | ||