qemu/hw/block
Jamin Lin 61f9376775 hw/block: m25p80: support quad mode for w25q01jvq
According to the w25q01jv datasheet at page 16,
it is required to set QE bit in "Status Register 2".
Besides, users are able to utilize "Write Status Register 1(0x01)"
command to set QE bit in "Status Register 2" and
utilize "Read Status Register 2(0x35)" command to get the QE bit status.

To support quad mode for w25q01jvq, update collecting data needed
2 bytes for WRSR command in decode_new_cmd function and
verify QE bit at the second byte of collecting data bit 2
in complete_collecting_data.

Update RDCR_EQIO command to set bit 2 of return data
if quad mode enable in decode_new_cmd.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-07-09 08:05:44 +02:00
..
dataplane
block.c
cdrom.c
ecc.c
fdc-internal.h
fdc-isa.c
fdc-sysbus.c
fdc.c
hd-geometry.c
Kconfig
m25p80_sfdp.c
m25p80_sfdp.h
m25p80.c hw/block: m25p80: support quad mode for w25q01jvq 2024-07-09 08:05:44 +02:00
meson.build
nand.c
onenand.c
pflash_cfi01.c
pflash_cfi02.c
swim.c
tc58128.c
trace-events
trace.h
vhost-user-blk.c
virtio-blk-common.c
virtio-blk.c
xen_blkif.h
xen-block.c