Peter Maydell b033cd3d00 target-arm: A64: Implement scalar three different instructions ...

Implement the scalar three different instruction group:
it only has three instructions in it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>

2014-02-20 10:35:49 +00:00

..

arm-semi.c

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cpu64.c

target-arm: Switch ARMCPUInfo arrays to use terminator entries

2014-01-14 10:09:04 +10:00

cpu-qom.h

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cpu.c

ARM: Convert MIDR to a property

2014-01-31 14:47:32 +00:00

cpu.h

target-arm: Move arm_rmode_to_sf to a shared location.

2014-01-31 14:47:33 +00:00

crypto_helper.c

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gdbstub64.c

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gdbstub.c

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helper-a64.c

target-arm: A64: Implement plain vector SIMD indexed element insns

2014-02-20 10:35:48 +00:00

helper-a64.h

target-arm: A64: Implement plain vector SIMD indexed element insns

2014-02-20 10:35:48 +00:00

helper.c

exec: Make stl_*_phys input an AddressSpace

2014-02-11 22:57:18 +10:00

helper.h

target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT

2014-02-08 14:47:28 +00:00

iwmmxt_helper.c

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kvm32.c

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kvm64.c

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kvm_arm.h

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kvm-consts.h

target-arm: Update generic cpreg code for AArch64

2014-01-04 22:15:44 +00:00

kvm-stub.c

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kvm.c

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machine.c

target-arm: Widen exclusive-access support struct fields to 64 bits

2014-01-08 19:07:20 +00:00

Makefile.objs

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neon_helper.c

target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT

2014-02-08 14:47:28 +00:00

op_addsub.h

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op_helper.c

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translate-a64.c

target-arm: A64: Implement scalar three different instructions

2014-02-20 10:35:49 +00:00

translate.c

target-arm: Add support for AArch32 64bit VCVTB and VCVTT

2014-02-08 14:47:28 +00:00

translate.h

target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder

2014-01-07 19:17:58 +00:00