aff8cee805
This pull request contains a handful of patches that I'd like to target for the 4.1 soft freeze. There are a handful of new features: * Support for the 1.11.0, the latest privileged specification. * Support for reading and writing the PRCI registers. * Better control over the ISA of the target machine. * Support for the cpu-topology device tree node. Additionally, there are a handful of bug fixes including: * Load reservations are now broken by both store conditional and by scheduling, which fixes issues with parallel applications. * Various fixes to the PMP implementation. * Fixes to the 32-bit linux-user syscall ABI. * Various fixes for instruction decodeing. * A fix to the PCI device tree "bus-range" property. This boots 32-bit and 64-bit OpenEmbedded. Changes since v2 [riscv-for-master-4.1-sf1-v2]: * Dropped OpenSBI. Changes since v1 [riscv-for-master-4.1-sf1]: * Contains a fix to the sifive_u OpenSBI integration. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAl0caa0THHBhbG1lckBk YWJiZWx0LmNvbQAKCRDvTKFQLMurQRTNEACwLeajFWIdeltz9PpzlmbABoY9p8rT amMVjEcisMmIzV7UjLcmqYAyPUFb2KvNy5EA15op0nQKGv7Mm7c4P7V5/eQyz9wE 9/81s3OoOuRa79mwgF3aekA6iQXb0ID+kMaIFSrbTTyECOULb2kb4/xxOH+N13wh 8VfYBdgxsvC37DDShXuzGOdtWpu1wZDgYwYOHAIns/r90FYA1w2vJhjn72AiDfnY QKwm6FHiplraMfbURRxbgU5oUIXsCelYNB3Fu9dFOuVwgmwrwFHJIG1Mi5pvMkbo vRnSDX5vKKpeyFj6U23RnCJpxoORe0Bp6GnD5MbByUr9oroBbD3dkNryXU0da5jN e5Jje3F8v/g3KdRUm6AQJb6JBBOZu4uSUn9jUfqlNLFDvUDLTq74kfJHLzsWr4Ds k/rP3fmyked27KnEwCOzAEEDI4Z3exbwnoPiP5ik92ZkSL7PVwLpWvB/8tn8HQab ldq8w/piUkbC9ug2p07TFg6aST8YjzuGHtOW4M8TpX5cuAiHPbjS54dj88+EL5i7 shBWFKEuKV0ESVgIBwJu9qlX5QvQWJA4LSo35PyrGJb6xV+lQ3j0pdcOojL6ZSkk JDbQtC1nsxDf/Qt4vHc4VbOZQChO+FYs2Smin8Wl5gN+hReY6lB/ZtHjYl7uw2bC 9Ijy2OkCjtz4mw== =lliO -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.1-sf1-v3' into staging RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 This pull request contains a handful of patches that I'd like to target for the 4.1 soft freeze. There are a handful of new features: * Support for the 1.11.0, the latest privileged specification. * Support for reading and writing the PRCI registers. * Better control over the ISA of the target machine. * Support for the cpu-topology device tree node. Additionally, there are a handful of bug fixes including: * Load reservations are now broken by both store conditional and by scheduling, which fixes issues with parallel applications. * Various fixes to the PMP implementation. * Fixes to the 32-bit linux-user syscall ABI. * Various fixes for instruction decodeing. * A fix to the PCI device tree "bus-range" property. This boots 32-bit and 64-bit OpenEmbedded. Changes since v2 [riscv-for-master-4.1-sf1-v2]: * Dropped OpenSBI. Changes since v1 [riscv-for-master-4.1-sf1]: * Contains a fix to the sifive_u OpenSBI integration. # gpg: Signature made Wed 03 Jul 2019 09:39:09 BST # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.1-sf1-v3: (32 commits) hw/riscv: Extend the kernel loading support hw/riscv: Add support for loading a firmware hw/riscv: Split out the boot functions riscv: sifive_u: Update the plic hart config to support multicore riscv: sifive_u: Do not create hard-coded phandles in DT disas/riscv: Fix `rdinstreth` constraint disas/riscv: Disassemble reserved compressed encodings as illegal riscv: virt: Add cpu-topology DT node. RISC-V: Update syscall list for 32-bit support. RISC-V: Clear load reservations on context switch and SC RISC-V: Add support for the Zicsr extension RISC-V: Add support for the Zifencei extension target/riscv: Add support for disabling/enabling Counters target/riscv: Remove user version information target/riscv: Require either I or E base extension qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 target/riscv: Set privledge spec 1.11.0 as default target/riscv: Add the mcountinhibit CSR target/riscv: Add the privledge spec version 1.11.0 target/riscv: Restructure deprecatd CPUs ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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