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qemu/target/mips
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Richard Henderson 157f75435e MIPS patches queue 
- Fine-grained MAINTAINERS sections
 - Fix MSA MADDV.B / MSUBV.B opcodes
 - Convert MSA opcodes to decodetree
 - Correct Loongson-3A4000 MSAIR register
 - Do not accept ELF nanoMIPS binaries on linux-user
 - Use ISA instead of PCI interrupts in VT82C686 PCI device
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Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into staging

MIPS patches queue

- Fine-grained MAINTAINERS sections
- Fix MSA MADDV.B / MSUBV.B opcodes
- Convert MSA opcodes to decodetree
- Correct Loongson-3A4000 MSAIR register
- Do not accept ELF nanoMIPS binaries on linux-user
- Use ISA instead of PCI interrupts in VT82C686 PCI device

# gpg: Signature made Tue 02 Nov 2021 09:41:04 AM EDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]

* remotes/philmd/tags/mips-20211102: (41 commits)
  Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too"
  hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts
  usb/uhci: Replace pci_set_irq with qemu_set_irq
  usb/uhci: Disallow user creating a vt82c686-uhci-pci device
  usb/uhci: Misc clean up
  target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU
  target/mips: Fix Loongson-3A4000 MSAIR config register
  target/mips: Remove one MSA unnecessary decodetree overlap group
  target/mips: Remove generic MSA opcode
  target/mips: Convert CTCMSA opcode to decodetree
  target/mips: Convert CFCMSA opcode to decodetree
  target/mips: Convert MSA MOVE.V opcode to decodetree
  target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
  target/mips: Convert MSA COPY_U opcode to decodetree
  target/mips: Convert MSA ELM instruction format to decodetree
  target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
  target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
  target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
  target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
  target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-11-02 15:12:11 -04:00
..
sysemu target/mips: Move CP0 helpers to sysemu/cp0.c 2021-05-02 16:49:35 +02:00
tcg MIPS patches queue 2021-11-02 15:12:11 -04:00
cpu-defs.c.inc target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU 2021-11-02 14:32:32 +01:00
cpu-param.h
cpu-qom.h target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed 2021-05-26 15:33:59 -07:00
cpu.c target/mips: Make mips_cpu_tlb_fill sysemu only 2021-11-02 07:00:52 -04:00
cpu.h include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
fpu_helper.h target/mips: Set set_default_nan_mode with set_snan_bit_is_one 2021-05-16 07:13:51 -05:00
fpu.c target/mips: Optimize CPU/FPU regnames[] arrays 2021-05-02 16:49:34 +02:00
gdbstub.c
helper.h target/mips: Extract NEC Vr54xx helper definitions 2021-08-25 13:02:14 +02:00
internal.h include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm_mips.h
kvm.c sysemu: Let VMChangeStateHandler take boolean 'running' argument 2021-03-09 23:13:57 +01:00
meson.build target/mips: Move TCG source files under tcg/ sub directory 2021-05-02 16:49:35 +02:00
mips-defs.h
msa.c target/mips: Move msa_reset() to new source file 2021-05-02 16:49:34 +02:00
TODO