Taylor Simpson af7f182127 Hexagon (target/hexagon) bit reverse (brev) addressing ... The following instructions are added L2_loadrub_pbr Rd32 = memub(Rx32++Mu2:brev) L2_loadrb_pbr Rd32 = memb(Rx32++Mu2:brev) L2_loadruh_pbr Rd32 = memuh(Rx32++Mu2:brev) L2_loadrh_pbr Rd32 = memh(Rx32++Mu2:brev) L2_loadri_pbr Rd32 = memw(Rx32++Mu2:brev) L2_loadrd_pbr Rdd32 = memd(Rx32++Mu2:brev) S2_storerb_pbr memb(Rx32++Mu2:brev).=.Rt32 S2_storerh_pbr memh(Rx32++Mu2:brev).=.Rt32 S2_storerf_pbr memh(Rx32++Mu2:brev).=.Rt.H32 S2_storeri_pbr memw(Rx32++Mu2:brev).=.Rt32 S2_storerd_pbr memd(Rx32++Mu2:brev).=.Rt32 S2_storerinew_pbr memw(Rx32++Mu2:brev).=.Nt8.new S2_storerbnew_pbr memw(Rx32++Mu2:brev).=.Nt8.new S2_storerhnew_pbr memw(Rx32++Mu2:brev).=.Nt8.new Test cases in tests/tcg/hexagon/brev.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-24-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2021-05-01 16:03:10 -07:00
..
allidefs.def
alu.idef	Hexagon (target/hexagon) add A4_addp_c/A4_subp_c	2021-05-01 08:31:43 -07:00
branch.idef
compare.idef	Hexagon (target/hexagon) cleanup ternary operators in semantics	2021-05-01 08:31:43 -07:00
encode_pp.def	Hexagon (target/hexagon) bit reverse (brev) addressing	2021-05-01 16:03:10 -07:00
encode_subinsn.def
encode.def
float.idef	Hexagon (target/hexagon) add F2_sfinvsqrta	2021-05-01 08:31:43 -07:00
iclass.def
ldst.idef	Hexagon (target/hexagon) bit reverse (brev) addressing	2021-05-01 16:03:10 -07:00
macros.def	Hexagon (target/hexagon) bit reverse (brev) addressing	2021-05-01 16:03:10 -07:00
mpy.idef
shift.idef
subinsns.idef
system.idef