qemu/hw/riscv
Anup Patel 18df0b4695 hw/riscv: virt: Allow creating multiple NUMA sockets
We extend RISC-V virt machine to allow creating a multi-socket
machine. Each RISC-V virt machine socket is a NUMA node having
a set of HARTs, a memory instance, a CLINT instance, and a PLIC
instance. Other devices are shared between all sockets. We also
update the generated device tree accordingly.

By default, NUMA multi-socket support is disabled for RISC-V virt
machine. To enable it, users can use "-numa" command-line options
of QEMU.

Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"

Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"

The maximum number of sockets in a RISC-V virt machine is 8
but this limit can be changed in future.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-6-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-08-25 09:11:35 -07:00
..
boot.c RISC-V: Support 64 bit start address 2020-07-13 17:25:37 -07:00
Kconfig hw/char: Initial commit of Ibex UART 2020-06-19 08:24:07 -07:00
meson.build hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
numa.c hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.c error: Eliminate error_propagate() with Coccinelle, part 1 2020-07-10 15:18:08 +02:00
riscv_hart.c riscv_hart: Fix riscv_harts_realize() error API violations 2020-07-02 06:25:29 +02:00
riscv_htif.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
sifive_clint.c hw/riscv: Allow creating multiple instances of CLINT 2020-08-25 09:11:35 -07:00
sifive_e_prci.c sysbus: Convert to sysbus_realize() etc. with Coccinelle 2020-06-15 22:05:28 +02:00
sifive_e.c hw/riscv: Allow creating multiple instances of PLIC 2020-08-25 09:11:35 -07:00
sifive_gpio.c hw/riscv: sifive_gpio: Do not blindly trigger output IRQs 2020-06-19 08:25:27 -07:00
sifive_plic.c hw/riscv: Allow creating multiple instances of PLIC 2020-08-25 09:11:35 -07:00
sifive_test.c sysbus: Convert to sysbus_realize() etc. with Coccinelle 2020-06-15 22:05:28 +02:00
sifive_u_otp.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
sifive_u_prci.c riscv: sifive: Implement PRCI model for FU540 2019-09-17 08:42:47 -07:00
sifive_u.c hw/riscv: Allow creating multiple instances of PLIC 2020-08-25 09:11:35 -07:00
sifive_uart.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
spike.c hw/riscv: spike: Allow creating multiple NUMA sockets 2020-08-25 09:11:35 -07:00
trace-events SiFive RISC-V GPIO Device 2019-05-24 11:58:30 -07:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
virt.c hw/riscv: virt: Allow creating multiple NUMA sockets 2020-08-25 09:11:35 -07:00