584acf34cb
The pixman library only supports blts with left to right, top to bottom order but the ATI VGA engine can also do different directions. Fix support for these via a temporary buffer for now. This fixes rendering issues related to such blts (such as moving windows) but some other glitches still remain. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-id: e21855faaeb30d7b1771f084f283f6a30bedb1a3.1562227303.git.balaton@eik.bme.hu Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
190 lines
7.7 KiB
C
190 lines
7.7 KiB
C
/*
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* QEMU ATI SVGA emulation
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* 2D engine functions
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*
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* Copyright (c) 2019 BALATON Zoltan
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*/
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#include "qemu/osdep.h"
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#include "ati_int.h"
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#include "ati_regs.h"
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#include "qemu/log.h"
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#include "ui/pixel_ops.h"
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/*
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* NOTE:
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* This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to
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* reinvent the wheel (unlikely to get better with a naive implementation than
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* existing libraries) and avoid (poorly) reimplementing gfx primitives.
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* That is unnecessary and would become a performance problem. Instead, try to
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* map to and reuse existing optimised facilities (e.g. pixman) wherever
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* possible.
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*/
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static int ati_bpp_from_datatype(ATIVGAState *s)
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{
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switch (s->regs.dp_datatype & 0xf) {
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case 2:
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return 8;
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case 3:
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case 4:
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return 16;
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case 5:
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return 24;
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case 6:
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return 32;
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default:
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qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n",
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s->regs.dp_datatype & 0xf);
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return 0;
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}
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}
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#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)
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void ati_2d_blt(ATIVGAState *s)
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{
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/* FIXME it is probably more complex than this and may need to be */
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/* rewritten but for now as a start just to get some output: */
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DisplaySurface *ds = qemu_console_surface(s->vga.con);
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DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr,
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s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),
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surface_bits_per_pixel(ds),
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(s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
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int dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
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s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width);
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int dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
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s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height);
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int bpp = ati_bpp_from_datatype(s);
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int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch;
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uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
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s->regs.dst_offset : s->regs.default_offset);
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if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
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dst_bits += s->regs.crtc_offset & 0x07ffffff;
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dst_stride *= bpp;
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}
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uint8_t *end = s->vga.vram_ptr + s->vga.vram_size;
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if (dst_bits >= end || dst_bits + dst_x + (dst_y + s->regs.dst_height) *
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dst_stride >= end) {
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qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
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return;
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}
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DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n",
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s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset,
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s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch,
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s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,
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s->regs.dst_width, s->regs.dst_height,
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(s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'),
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(s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^'));
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switch (s->regs.dp_mix & GMC_ROP3_MASK) {
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case ROP3_SRCCOPY:
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{
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int src_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
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s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width);
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int src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
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s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height);
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int src_stride = DEFAULT_CNTL ?
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s->regs.src_pitch : s->regs.default_pitch;
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uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
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s->regs.src_offset : s->regs.default_offset);
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if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
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src_bits += s->regs.crtc_offset & 0x07ffffff;
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src_stride *= bpp;
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}
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if (src_bits >= end || src_bits + src_x +
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(src_y + s->regs.dst_height) * src_stride >= end) {
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qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
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return;
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}
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src_stride /= sizeof(uint32_t);
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dst_stride /= sizeof(uint32_t);
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DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n",
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src_bits, dst_bits, src_stride, dst_stride, bpp, bpp,
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src_x, src_y, dst_x, dst_y,
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s->regs.dst_width, s->regs.dst_height);
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if (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT &&
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s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) {
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pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits,
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src_stride, dst_stride, bpp, bpp,
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src_x, src_y, dst_x, dst_y,
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s->regs.dst_width, s->regs.dst_height);
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} else {
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/* FIXME: We only really need a temporary if src and dst overlap */
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int llb = s->regs.dst_width * (bpp / 8);
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int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t));
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uint32_t *tmp = g_malloc(tmp_stride * sizeof(uint32_t) *
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s->regs.dst_height);
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pixman_blt((uint32_t *)src_bits, tmp,
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src_stride, tmp_stride, bpp, bpp,
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src_x, src_y, 0, 0,
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s->regs.dst_width, s->regs.dst_height);
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pixman_blt(tmp, (uint32_t *)dst_bits,
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tmp_stride, dst_stride, bpp, bpp,
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0, 0, dst_x, dst_y,
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s->regs.dst_width, s->regs.dst_height);
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g_free(tmp);
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}
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if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
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dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
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s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
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memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
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s->regs.dst_offset +
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dst_y * surface_stride(ds),
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s->regs.dst_height * surface_stride(ds));
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}
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s->regs.dst_x += s->regs.dst_width;
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s->regs.dst_y += s->regs.dst_height;
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break;
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}
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case ROP3_PATCOPY:
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case ROP3_BLACKNESS:
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case ROP3_WHITENESS:
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{
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uint32_t filler = 0;
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switch (s->regs.dp_mix & GMC_ROP3_MASK) {
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case ROP3_PATCOPY:
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filler = s->regs.dp_brush_frgd_clr;
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break;
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case ROP3_BLACKNESS:
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filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[0],
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s->vga.palette[1], s->vga.palette[2]);
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break;
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case ROP3_WHITENESS:
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filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[3],
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s->vga.palette[4], s->vga.palette[5]);
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break;
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}
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dst_stride /= sizeof(uint32_t);
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DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n",
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dst_bits, dst_stride, bpp,
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s->regs.dst_x, s->regs.dst_y,
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s->regs.dst_width, s->regs.dst_height,
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filler);
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pixman_fill((uint32_t *)dst_bits, dst_stride, bpp,
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s->regs.dst_x, s->regs.dst_y,
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s->regs.dst_width, s->regs.dst_height,
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filler);
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if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
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dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
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s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
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memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
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s->regs.dst_offset +
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dst_y * surface_stride(ds),
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s->regs.dst_height * surface_stride(ds));
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}
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s->regs.dst_y += s->regs.dst_height;
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break;
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}
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default:
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qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n",
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(s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
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}
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}
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