qemu/target
Daniel Henrique Barboza aeb2bc5950 qapi,risc-v: add query-cpu-model-expansion
This API is used to inspect the characteristics of a given CPU model. It
also allows users to validate a CPU model with a certain configuration,
e.g. if "-cpu X,a=true,b=false" is a valid setup for a given QEMU
binary. We'll start implementing the first part. The second requires
more changes in RISC-V CPU boot flow.

The implementation is inspired by the existing ARM
query-cpu-model-expansion impl in target/arm/arm-qmp-cmds.c. We'll
create a RISCVCPU object with the required model, fetch its existing
properties, add a couple of relevant boolean options (pmp and mmu) and
display it to users.

Here's an usage example:

./build/qemu-system-riscv64 -S -M virt -display none \
  -qmp  tcp:localhost:1234,server,wait=off

./scripts/qmp/qmp-shell localhost:1234
Welcome to the QMP low-level shell!
Connected to QEMU 8.1.50

(QEMU)  query-cpu-model-expansion type=full model={"name":"rv64"}
{"return": {"model": {"name": "rv64", "props": {"zicond": false, "x-zvfh": false, "mmu": true, "x-zvfbfwma": false, "x-zvfbfmin": false, "xtheadbs": false, "xtheadbb": false, "xtheadba": false, "xtheadmemidx": false, "smstateen": false, "zfinx": false, "Zve64f": false, "Zve32f": false, "x-zvfhmin": false, "xventanacondops": false, "xtheadcondmov": false, "svpbmt": false, "zbs": true, "zbc": true, "zbb": true, "zba": true, "zicboz": true, "xtheadmac": false, "Zfh": false, "Zfa": true, "zbkx": false, "zbkc": false, "zbkb": false, "Zve64d": false, "x-zfbfmin": false, "zk": false, "x-epmp": false, "xtheadmempair": false, "zkt": false, "zks": false, "zkr": false, "zkn": false, "Zfhmin": false, "zksh": false, "zknh": false, "zkne": false, "zknd": false, "zhinx": false, "Zicsr": true, "sscofpmf": false, "Zihintntl": true, "sstc": true, "xtheadcmo": false, "x-zvbb": false, "zksed": false, "x-zvkned": false, "xtheadsync": false, "x-zvkg": false, "zhinxmin": false, "svadu": true, "xtheadfmv": false, "x-zvksed": false, "svnapot": false, "pmp": true, "x-zvknhb": false, "x-zvknha": false, "xtheadfmemidx": false, "x-zvksh": false, "zdinx": false, "zicbom": true, "Zihintpause": true, "svinval": false, "zcf": false, "zce": false, "zcd": false, "zcb": false, "zca": false, "x-ssaia": false, "x-smaia": false, "zmmul": false, "x-zvbc": false, "Zifencei": true, "zcmt": false, "zcmp": false, "Zawrs": true}}}}

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231018195638.211151-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-07 11:06:01 +10:00
..
alpha meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
arm target/arm: Correctly propagate stage 1 BTI guarded bit in a two-stage walk 2023-11-02 13:36:45 +00:00
avr meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
cris meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
hexagon target/hexagon: fix some occurrences of -Wshadow=local 2023-10-18 16:56:17 -07:00
hppa meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
i386 kvm: i8254: require KVM_CAP_PIT2 and KVM_CAP_PIT_STATE2 2023-10-25 19:53:38 +02:00
loongarch linux-user/loongarch64: Use traps to track LSX/LASX usage 2023-11-03 14:13:18 +08:00
m68k target/m68k: Use tcg_gen_ext_i32 2023-10-22 16:43:52 -07:00
microblaze meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
mips hw/misc/mips_itu: Declare itc_reconfigure() in 'hw/misc/mips_itu.h' 2023-10-19 23:13:27 +02:00
nios2 meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
openrisc meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
ppc target/ppc: Remove references to gdb_has_xml 2023-10-11 08:46:33 +01:00
riscv qapi,risc-v: add query-cpu-model-expansion 2023-11-07 11:06:01 +10:00
rx target/rx: Use tcg_gen_ext_i32 2023-10-22 16:43:53 -07:00
s390x target/s390x/kvm: Simplify the GPRs, ACRs, CRs and prefix synchronization code 2023-10-20 07:16:53 +02:00
sh4 target/sh4: Disable decode_gusa when plugins enabled 2023-10-11 08:46:36 +01:00
sparc target/sparc: Check for invalid cond in gen_compare_reg 2023-11-05 12:07:21 -08:00
tricore target/tricore: Use tcg_gen_*extract_tl 2023-10-22 16:44:42 -07:00
xtensa target/xtensa: Use tcg_gen_sextract_i32 2023-10-22 16:44:49 -07:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00