62b9cf0a77
Move the m48t59 device away from using old_mmio MemoryRegionOps accessors. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20180802180602.22047-1-peter.maydell@linaro.org
718 lines
19 KiB
C
718 lines
19 KiB
C
/*
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* QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
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*
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* Copyright (c) 2003-2005, 2007, 2017 Jocelyn Mayer
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* Copyright (c) 2013 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/timer/m48t59.h"
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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#include "hw/sysbus.h"
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#include "exec/address-spaces.h"
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#include "qemu/bcd.h"
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#include "m48t59-internal.h"
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#define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
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#define M48TXX_SYS_BUS_GET_CLASS(obj) \
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OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
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#define M48TXX_SYS_BUS_CLASS(klass) \
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OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
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#define M48TXX_SYS_BUS(obj) \
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OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
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/*
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* Chipset docs:
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* http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
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* http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
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* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
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*/
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typedef struct M48txxSysBusState {
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SysBusDevice parent_obj;
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M48t59State state;
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MemoryRegion io;
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} M48txxSysBusState;
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typedef struct M48txxSysBusDeviceClass {
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SysBusDeviceClass parent_class;
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M48txxInfo info;
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} M48txxSysBusDeviceClass;
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static M48txxInfo m48txx_sysbus_info[] = {
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{
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.bus_name = "sysbus-m48t02",
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.model = 2,
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.size = 0x800,
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},{
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.bus_name = "sysbus-m48t08",
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.model = 8,
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.size = 0x2000,
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},{
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.bus_name = "sysbus-m48t59",
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.model = 59,
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.size = 0x2000,
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}
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};
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/* Fake timer functions */
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/* Alarm management */
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static void alarm_cb (void *opaque)
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{
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struct tm tm;
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uint64_t next_time;
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M48t59State *NVRAM = opaque;
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qemu_set_irq(NVRAM->IRQ, 1);
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if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once a month */
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qemu_get_timedate(&tm, NVRAM->time_offset);
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tm.tm_mon++;
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if (tm.tm_mon == 13) {
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tm.tm_mon = 1;
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tm.tm_year++;
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}
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next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once a day */
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next_time = 24 * 60 * 60;
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once an hour */
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next_time = 60 * 60;
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} else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
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(NVRAM->buffer[0x1FF2] & 0x80) == 0) {
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/* Repeat once a minute */
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next_time = 60;
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} else {
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/* Repeat once a second */
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next_time = 1;
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}
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timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +
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next_time * 1000);
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qemu_set_irq(NVRAM->IRQ, 0);
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}
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static void set_alarm(M48t59State *NVRAM)
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{
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int diff;
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if (NVRAM->alrm_timer != NULL) {
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timer_del(NVRAM->alrm_timer);
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diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
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if (diff > 0)
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timer_mod(NVRAM->alrm_timer, diff * 1000);
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}
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}
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/* RTC management helpers */
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static inline void get_time(M48t59State *NVRAM, struct tm *tm)
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{
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qemu_get_timedate(tm, NVRAM->time_offset);
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}
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static void set_time(M48t59State *NVRAM, struct tm *tm)
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{
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NVRAM->time_offset = qemu_timedate_diff(tm);
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set_alarm(NVRAM);
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}
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/* Watchdog management */
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static void watchdog_cb (void *opaque)
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{
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M48t59State *NVRAM = opaque;
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NVRAM->buffer[0x1FF0] |= 0x80;
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if (NVRAM->buffer[0x1FF7] & 0x80) {
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NVRAM->buffer[0x1FF7] = 0x00;
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NVRAM->buffer[0x1FFC] &= ~0x40;
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/* May it be a hw CPU Reset instead ? */
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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} else {
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qemu_set_irq(NVRAM->IRQ, 1);
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qemu_set_irq(NVRAM->IRQ, 0);
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}
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}
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static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
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{
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uint64_t interval; /* in 1/16 seconds */
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NVRAM->buffer[0x1FF0] &= ~0x80;
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if (NVRAM->wd_timer != NULL) {
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timer_del(NVRAM->wd_timer);
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if (value != 0) {
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interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
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timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
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((interval * 1000) >> 4));
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}
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}
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}
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/* Direct access to NVRAM */
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void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
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{
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struct tm tm;
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int tmp;
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if (addr > 0x1FF8 && addr < 0x2000)
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NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
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/* check for NVRAM access */
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if ((NVRAM->model == 2 && addr < 0x7f8) ||
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(NVRAM->model == 8 && addr < 0x1ff8) ||
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(NVRAM->model == 59 && addr < 0x1ff0)) {
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goto do_write;
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}
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/* TOD access */
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switch (addr) {
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case 0x1FF0:
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/* flags register : read-only */
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break;
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case 0x1FF1:
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/* unused */
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break;
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case 0x1FF2:
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/* alarm seconds */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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NVRAM->alarm.tm_sec = tmp;
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NVRAM->buffer[0x1FF2] = val;
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set_alarm(NVRAM);
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}
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break;
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case 0x1FF3:
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/* alarm minutes */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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NVRAM->alarm.tm_min = tmp;
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NVRAM->buffer[0x1FF3] = val;
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set_alarm(NVRAM);
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}
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break;
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case 0x1FF4:
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/* alarm hours */
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tmp = from_bcd(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) {
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NVRAM->alarm.tm_hour = tmp;
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NVRAM->buffer[0x1FF4] = val;
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set_alarm(NVRAM);
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}
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break;
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case 0x1FF5:
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/* alarm date */
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tmp = from_bcd(val & 0x3F);
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if (tmp != 0) {
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NVRAM->alarm.tm_mday = tmp;
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NVRAM->buffer[0x1FF5] = val;
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set_alarm(NVRAM);
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}
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break;
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case 0x1FF6:
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/* interrupts */
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NVRAM->buffer[0x1FF6] = val;
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break;
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case 0x1FF7:
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/* watchdog */
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NVRAM->buffer[0x1FF7] = val;
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set_up_watchdog(NVRAM, val);
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break;
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case 0x1FF8:
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case 0x07F8:
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/* control */
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NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
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break;
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case 0x1FF9:
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case 0x07F9:
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/* seconds (BCD) */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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get_time(NVRAM, &tm);
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tm.tm_sec = tmp;
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set_time(NVRAM, &tm);
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}
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if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
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if (val & 0x80) {
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NVRAM->stop_time = time(NULL);
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} else {
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NVRAM->time_offset += NVRAM->stop_time - time(NULL);
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NVRAM->stop_time = 0;
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}
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}
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NVRAM->buffer[addr] = val & 0x80;
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break;
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case 0x1FFA:
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case 0x07FA:
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/* minutes (BCD) */
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tmp = from_bcd(val & 0x7F);
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if (tmp >= 0 && tmp <= 59) {
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get_time(NVRAM, &tm);
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tm.tm_min = tmp;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFB:
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case 0x07FB:
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/* hours (BCD) */
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tmp = from_bcd(val & 0x3F);
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if (tmp >= 0 && tmp <= 23) {
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get_time(NVRAM, &tm);
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tm.tm_hour = tmp;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFC:
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case 0x07FC:
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/* day of the week / century */
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tmp = from_bcd(val & 0x07);
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get_time(NVRAM, &tm);
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tm.tm_wday = tmp;
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set_time(NVRAM, &tm);
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NVRAM->buffer[addr] = val & 0x40;
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break;
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case 0x1FFD:
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case 0x07FD:
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/* date (BCD) */
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tmp = from_bcd(val & 0x3F);
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if (tmp != 0) {
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get_time(NVRAM, &tm);
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tm.tm_mday = tmp;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFE:
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case 0x07FE:
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/* month */
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tmp = from_bcd(val & 0x1F);
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if (tmp >= 1 && tmp <= 12) {
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get_time(NVRAM, &tm);
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tm.tm_mon = tmp - 1;
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set_time(NVRAM, &tm);
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}
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break;
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case 0x1FFF:
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case 0x07FF:
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/* year */
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tmp = from_bcd(val);
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if (tmp >= 0 && tmp <= 99) {
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get_time(NVRAM, &tm);
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tm.tm_year = from_bcd(val) + NVRAM->base_year - 1900;
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set_time(NVRAM, &tm);
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}
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break;
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default:
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/* Check lock registers state */
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if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
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break;
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if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
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break;
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do_write:
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if (addr < NVRAM->size) {
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NVRAM->buffer[addr] = val & 0xFF;
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}
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break;
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}
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}
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uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
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{
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struct tm tm;
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uint32_t retval = 0xFF;
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/* check for NVRAM access */
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if ((NVRAM->model == 2 && addr < 0x078f) ||
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(NVRAM->model == 8 && addr < 0x1ff8) ||
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(NVRAM->model == 59 && addr < 0x1ff0)) {
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goto do_read;
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}
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/* TOD access */
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switch (addr) {
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case 0x1FF0:
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/* flags register */
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goto do_read;
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case 0x1FF1:
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/* unused */
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retval = 0;
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break;
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case 0x1FF2:
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/* alarm seconds */
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goto do_read;
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case 0x1FF3:
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/* alarm minutes */
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goto do_read;
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case 0x1FF4:
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/* alarm hours */
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goto do_read;
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case 0x1FF5:
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/* alarm date */
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goto do_read;
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case 0x1FF6:
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/* interrupts */
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goto do_read;
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case 0x1FF7:
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/* A read resets the watchdog */
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set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
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goto do_read;
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case 0x1FF8:
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case 0x07F8:
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/* control */
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goto do_read;
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case 0x1FF9:
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case 0x07F9:
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/* seconds (BCD) */
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get_time(NVRAM, &tm);
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retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
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break;
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case 0x1FFA:
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case 0x07FA:
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/* minutes (BCD) */
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get_time(NVRAM, &tm);
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retval = to_bcd(tm.tm_min);
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break;
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case 0x1FFB:
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case 0x07FB:
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/* hours (BCD) */
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get_time(NVRAM, &tm);
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retval = to_bcd(tm.tm_hour);
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break;
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case 0x1FFC:
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case 0x07FC:
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/* day of the week / century */
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get_time(NVRAM, &tm);
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retval = NVRAM->buffer[addr] | tm.tm_wday;
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break;
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case 0x1FFD:
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case 0x07FD:
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/* date */
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get_time(NVRAM, &tm);
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retval = to_bcd(tm.tm_mday);
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break;
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case 0x1FFE:
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case 0x07FE:
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/* month */
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get_time(NVRAM, &tm);
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retval = to_bcd(tm.tm_mon + 1);
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break;
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case 0x1FFF:
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case 0x07FF:
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/* year */
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get_time(NVRAM, &tm);
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retval = to_bcd((tm.tm_year + 1900 - NVRAM->base_year) % 100);
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break;
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default:
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/* Check lock registers state */
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if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
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break;
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if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
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break;
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do_read:
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if (addr < NVRAM->size) {
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retval = NVRAM->buffer[addr];
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}
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break;
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}
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if (addr > 0x1FF9 && addr < 0x2000)
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NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
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return retval;
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}
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/* IO access to NVRAM */
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static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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M48t59State *NVRAM = opaque;
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NVRAM_PRINTF("%s: 0x%"HWADDR_PRIx" => 0x%"PRIx64"\n", __func__, addr, val);
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switch (addr) {
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case 0:
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NVRAM->addr &= ~0x00FF;
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NVRAM->addr |= val;
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break;
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case 1:
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NVRAM->addr &= ~0xFF00;
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NVRAM->addr |= val << 8;
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break;
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case 3:
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m48t59_write(NVRAM, NVRAM->addr, val);
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NVRAM->addr = 0x0000;
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break;
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default:
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break;
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}
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}
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static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)
|
|
{
|
|
M48t59State *NVRAM = opaque;
|
|
uint32_t retval;
|
|
|
|
switch (addr) {
|
|
case 3:
|
|
retval = m48t59_read(NVRAM, NVRAM->addr);
|
|
break;
|
|
default:
|
|
retval = -1;
|
|
break;
|
|
}
|
|
NVRAM_PRINTF("%s: 0x%"HWADDR_PRIx" <= 0x%08x\n", __func__, addr, retval);
|
|
|
|
return retval;
|
|
}
|
|
|
|
static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size)
|
|
{
|
|
M48t59State *NVRAM = opaque;
|
|
|
|
return m48t59_read(NVRAM, addr);
|
|
}
|
|
|
|
static void nvram_write(void *opaque, hwaddr addr, uint64_t value,
|
|
unsigned size)
|
|
{
|
|
M48t59State *NVRAM = opaque;
|
|
|
|
return m48t59_write(NVRAM, addr, value);
|
|
}
|
|
|
|
static const MemoryRegionOps nvram_ops = {
|
|
.read = nvram_read,
|
|
.write = nvram_write,
|
|
.impl.min_access_size = 1,
|
|
.impl.max_access_size = 1,
|
|
.valid.min_access_size = 1,
|
|
.valid.max_access_size = 4,
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
|
};
|
|
|
|
static const VMStateDescription vmstate_m48t59 = {
|
|
.name = "m48t59",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT8(lock, M48t59State),
|
|
VMSTATE_UINT16(addr, M48t59State),
|
|
VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, size),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
void m48t59_reset_common(M48t59State *NVRAM)
|
|
{
|
|
NVRAM->addr = 0;
|
|
NVRAM->lock = 0;
|
|
if (NVRAM->alrm_timer != NULL)
|
|
timer_del(NVRAM->alrm_timer);
|
|
|
|
if (NVRAM->wd_timer != NULL)
|
|
timer_del(NVRAM->wd_timer);
|
|
}
|
|
|
|
static void m48t59_reset_sysbus(DeviceState *d)
|
|
{
|
|
M48txxSysBusState *sys = M48TXX_SYS_BUS(d);
|
|
M48t59State *NVRAM = &sys->state;
|
|
|
|
m48t59_reset_common(NVRAM);
|
|
}
|
|
|
|
const MemoryRegionOps m48t59_io_ops = {
|
|
.read = NVRAM_readb,
|
|
.write = NVRAM_writeb,
|
|
.impl = {
|
|
.min_access_size = 1,
|
|
.max_access_size = 1,
|
|
},
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
};
|
|
|
|
/* Initialisation routine */
|
|
Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
|
|
uint32_t io_base, uint16_t size, int base_year,
|
|
int model)
|
|
{
|
|
DeviceState *dev;
|
|
SysBusDevice *s;
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) {
|
|
if (m48txx_sysbus_info[i].size != size ||
|
|
m48txx_sysbus_info[i].model != model) {
|
|
continue;
|
|
}
|
|
|
|
dev = qdev_create(NULL, m48txx_sysbus_info[i].bus_name);
|
|
qdev_prop_set_int32(dev, "base-year", base_year);
|
|
qdev_init_nofail(dev);
|
|
s = SYS_BUS_DEVICE(dev);
|
|
sysbus_connect_irq(s, 0, IRQ);
|
|
if (io_base != 0) {
|
|
memory_region_add_subregion(get_system_io(), io_base,
|
|
sysbus_mmio_get_region(s, 1));
|
|
}
|
|
if (mem_base != 0) {
|
|
sysbus_mmio_map(s, 0, mem_base);
|
|
}
|
|
|
|
return NVRAM(s);
|
|
}
|
|
|
|
assert(false);
|
|
return NULL;
|
|
}
|
|
|
|
void m48t59_realize_common(M48t59State *s, Error **errp)
|
|
{
|
|
s->buffer = g_malloc0(s->size);
|
|
if (s->model == 59) {
|
|
s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);
|
|
s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
|
|
}
|
|
qemu_get_timedate(&s->alarm, 0);
|
|
}
|
|
|
|
static void m48t59_init1(Object *obj)
|
|
{
|
|
M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(obj);
|
|
M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
|
|
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
|
|
M48t59State *s = &d->state;
|
|
|
|
s->model = u->info.model;
|
|
s->size = u->info.size;
|
|
sysbus_init_irq(dev, &s->IRQ);
|
|
|
|
memory_region_init_io(&s->iomem, obj, &nvram_ops, s, "m48t59.nvram",
|
|
s->size);
|
|
memory_region_init_io(&d->io, obj, &m48t59_io_ops, s, "m48t59", 4);
|
|
}
|
|
|
|
static void m48t59_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
|
|
M48t59State *s = &d->state;
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
sysbus_init_mmio(sbd, &d->io);
|
|
m48t59_realize_common(s, errp);
|
|
}
|
|
|
|
static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr)
|
|
{
|
|
M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
|
|
return m48t59_read(&d->state, addr);
|
|
}
|
|
|
|
static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val)
|
|
{
|
|
M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
|
|
m48t59_write(&d->state, addr, val);
|
|
}
|
|
|
|
static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock)
|
|
{
|
|
M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
|
|
m48t59_toggle_lock(&d->state, lock);
|
|
}
|
|
|
|
static Property m48t59_sysbus_properties[] = {
|
|
DEFINE_PROP_INT32("base-year", M48txxSysBusState, state.base_year, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
NvramClass *nc = NVRAM_CLASS(klass);
|
|
|
|
dc->realize = m48t59_realize;
|
|
dc->reset = m48t59_reset_sysbus;
|
|
dc->props = m48t59_sysbus_properties;
|
|
dc->vmsd = &vmstate_m48t59;
|
|
nc->read = m48txx_sysbus_read;
|
|
nc->write = m48txx_sysbus_write;
|
|
nc->toggle_lock = m48txx_sysbus_toggle_lock;
|
|
}
|
|
|
|
static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass);
|
|
M48txxInfo *info = data;
|
|
|
|
u->info = *info;
|
|
}
|
|
|
|
static const TypeInfo nvram_info = {
|
|
.name = TYPE_NVRAM,
|
|
.parent = TYPE_INTERFACE,
|
|
.class_size = sizeof(NvramClass),
|
|
};
|
|
|
|
static const TypeInfo m48txx_sysbus_type_info = {
|
|
.name = TYPE_M48TXX_SYS_BUS,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(M48txxSysBusState),
|
|
.instance_init = m48t59_init1,
|
|
.abstract = true,
|
|
.class_init = m48txx_sysbus_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_NVRAM },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static void m48t59_register_types(void)
|
|
{
|
|
TypeInfo sysbus_type_info = {
|
|
.parent = TYPE_M48TXX_SYS_BUS,
|
|
.class_size = sizeof(M48txxSysBusDeviceClass),
|
|
.class_init = m48txx_sysbus_concrete_class_init,
|
|
};
|
|
int i;
|
|
|
|
type_register_static(&nvram_info);
|
|
type_register_static(&m48txx_sysbus_type_info);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) {
|
|
sysbus_type_info.name = m48txx_sysbus_info[i].bus_name;
|
|
sysbus_type_info.class_data = &m48txx_sysbus_info[i];
|
|
type_register(&sysbus_type_info);
|
|
}
|
|
}
|
|
|
|
type_init(m48t59_register_types)
|