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insn_trans
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target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
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2022-09-27 11:23:57 +10:00 |
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arch_dump.c
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dump: Replace opaque DumpState pointer with a typed one
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2022-10-06 19:30:43 +04:00 |
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bitmanip_helper.c
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target/riscv: rvk: add support for zbkx extension
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2022-04-29 10:47:45 +10:00 |
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common-semi-target.h
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semihosting: Split out common-semi-target.h
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2022-06-28 04:35:07 +05:30 |
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cpu_bits.h
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target/riscv: debug: Introduce tinfo CSR
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2022-09-27 11:23:57 +10:00 |
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cpu_helper.c
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target/riscv: Honour -semihosting-config userspace=on and enable=on
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2022-09-13 17:18:21 +01:00 |
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cpu_user.h
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cpu-param.h
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Normalize header guard symbol definition
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2022-05-11 16:50:26 +02:00 |
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cpu.c
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target/riscv: Convert to tcg_ops restore_state_to_opc
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2022-10-26 11:11:28 +10:00 |
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cpu.h
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dump: Replace opaque DumpState pointer with a typed one
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2022-10-06 19:30:43 +04:00 |
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crypto_helper.c
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target/riscv: rvk: add support for zksed/zksh extension
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2022-04-29 10:47:45 +10:00 |
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csr.c
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target/riscv: debug: Introduce tinfo CSR
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2022-09-27 11:23:57 +10:00 |
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debug.c
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target/riscv: debug: Add initial support of type 6 trigger
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2022-09-27 11:23:57 +10:00 |
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debug.h
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target/riscv: debug: Add initial support of type 6 trigger
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2022-09-27 11:23:57 +10:00 |
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fpu_helper.c
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target/riscv: add support for zhinx/zhinxmin
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2022-03-03 13:14:50 +10:00 |
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gdbstub.c
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target/riscv: Check the correct exception cause in vector GDB stub
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2022-09-27 07:04:38 +10:00 |
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helper.h
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target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
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2022-09-27 11:23:57 +10:00 |
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insn16.decode
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target/riscv: fix shifts shamt value for rv128c
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2022-09-07 09:18:32 +02:00 |
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insn32.decode
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target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
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2022-09-27 11:23:57 +10:00 |
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instmap.h
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target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
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2022-09-07 09:18:32 +02:00 |
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internals.h
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target/riscv: rvv: Add mask agnostic for vv instructions
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2022-09-07 09:18:32 +02:00 |
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Kconfig
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meson: Introduce target-specific Kconfig
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2021-07-09 18:21:34 +02:00 |
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kvm_riscv.h
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target/riscv: Support setting external interrupt by KVM
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2022-01-21 15:52:56 +10:00 |
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kvm-stub.c
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target/riscv: Support setting external interrupt by KVM
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2022-01-21 15:52:56 +10:00 |
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kvm.c
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kvm: allow target-specific accelerator properties
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2022-10-10 09:23:16 +02:00 |
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m128_helper.c
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target/riscv: support for 128-bit M extension
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2022-01-08 15:46:10 +10:00 |
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machine.c
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target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
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2022-09-27 11:23:57 +10:00 |
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meson.build
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target/riscv: Add stimecmp support
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2022-09-07 09:19:15 +02:00 |
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monitor.c
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target/riscv: Fix incorrect PTE merge in walk_pte
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2022-04-29 10:47:46 +10:00 |
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op_helper.c
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target/riscv: rvk: add CSR support for Zkr
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2022-04-29 10:47:45 +10:00 |
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pmp.c
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target/riscv: pmp: Fixup TLB size calculation
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2022-10-14 14:36:19 +10:00 |
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pmp.h
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target/riscv: rvk: add CSR support for Zkr
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2022-04-29 10:47:45 +10:00 |
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pmu.c
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hw/riscv: virt: Add PMU DT node to the device tree
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2022-09-07 09:19:15 +02:00 |
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pmu.h
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hw/riscv: virt: Add PMU DT node to the device tree
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2022-09-07 09:19:15 +02:00 |
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sbi_ecall_interface.h
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Clean up ill-advised or unusual header guards
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2022-05-11 16:50:01 +02:00 |
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time_helper.c
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target/riscv: Add vstimecmp support
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2022-09-07 09:19:15 +02:00 |
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time_helper.h
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target/riscv: Add stimecmp support
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2022-09-07 09:19:15 +02:00 |
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trace-events
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target/riscv: Add ePMP CSR access functions
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2021-05-11 20:02:06 +10:00 |
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trace.h
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trace: switch position of headers to what Meson requires
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2020-08-21 06:18:24 -04:00 |
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translate.c
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target/riscv: Honour -semihosting-config userspace=on and enable=on
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2022-09-13 17:18:21 +01:00 |
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vector_helper.c
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target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
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2022-09-27 11:23:57 +10:00 |
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XVentanaCondOps.decode
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target/riscv: Add XVentanaCondOps custom extension
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2022-02-16 12:24:18 +10:00 |
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