958e1dd130
Many instructions which load/store 128-bit values are supposed to raise #GP when the memory operand isn't 16-byte aligned. This includes: - Instructions explicitly requiring memory alignment (Exceptions Type 1 in the "AVX and SSE Instruction Exception Specification" section of the SDM) - Legacy SSE instructions that load/store 128-bit values (Exceptions Types 2 and 4). This change sets MO_ALIGN_16 on 128-bit memory accesses that require 16-byte alignment. It adds cpu_record_sigbus and cpu_do_unaligned_access hooks that simulate a #GP exception in qemu-user and qemu-system, respectively. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/217 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ricky Zhou <ricky@rzhou.org> Message-Id: <20220830034816.57091-2-ricky@rzhou.org> [Do not bother checking PREFIX_VEX, since AVX is not supported. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
117 lines
4.0 KiB
C
117 lines
4.0 KiB
C
/*
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* TCG specific prototypes for helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef I386_HELPER_TCG_H
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#define I386_HELPER_TCG_H
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#include "exec/exec-all.h"
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/* Maximum instruction code size */
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#define TARGET_MAX_INSN_SIZE 16
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#if defined(TARGET_X86_64)
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# define TCG_PHYS_ADDR_BITS 40
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#else
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# define TCG_PHYS_ADDR_BITS 36
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#endif
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QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS);
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/**
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* x86_cpu_do_interrupt:
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* @cpu: vCPU the interrupt is to be handled by.
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*/
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void x86_cpu_do_interrupt(CPUState *cpu);
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#ifndef CONFIG_USER_ONLY
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bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
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#endif
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void breakpoint_handler(CPUState *cs);
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/* n must be a constant to be efficient */
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static inline target_long lshift(target_long x, int n)
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{
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if (n >= 0) {
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return x << n;
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} else {
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return x >> (-n);
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}
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}
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/* translate.c */
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void tcg_x86_init(void);
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/* excp_helper.c */
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G_NORETURN void raise_exception(CPUX86State *env, int exception_index);
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G_NORETURN void raise_exception_ra(CPUX86State *env, int exception_index,
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uintptr_t retaddr);
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G_NORETURN void raise_exception_err(CPUX86State *env, int exception_index,
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int error_code);
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G_NORETURN void raise_exception_err_ra(CPUX86State *env, int exception_index,
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int error_code, uintptr_t retaddr);
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G_NORETURN void raise_interrupt(CPUX86State *nenv, int intno, int is_int,
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int error_code, int next_eip_addend);
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G_NORETURN void handle_unaligned_access(CPUX86State *env, vaddr vaddr,
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MMUAccessType access_type,
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uintptr_t retaddr);
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#ifdef CONFIG_USER_ONLY
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void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr,
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MMUAccessType access_type,
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bool maperr, uintptr_t ra);
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void x86_cpu_record_sigbus(CPUState *cs, vaddr addr,
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MMUAccessType access_type, uintptr_t ra);
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#else
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bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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G_NORETURN void x86_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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#endif
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/* cc_helper.c */
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extern const uint8_t parity_table[256];
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/* misc_helper.c */
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void cpu_load_eflags(CPUX86State *env, int eflags, int update_mask);
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G_NORETURN void do_pause(CPUX86State *env);
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/* sysemu/svm_helper.c */
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#ifndef CONFIG_USER_ONLY
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G_NORETURN void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
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uint64_t exit_info_1, uintptr_t retaddr);
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void do_vmexit(CPUX86State *env);
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#endif
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/* seg_helper.c */
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void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
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void do_interrupt_all(X86CPU *cpu, int intno, int is_int,
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int error_code, target_ulong next_eip, int is_hw);
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void handle_even_inj(CPUX86State *env, int intno, int is_int,
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int error_code, int is_hw, int rm);
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int exception_has_error_code(int intno);
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/* smm_helper.c */
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void do_smm_enter(X86CPU *cpu);
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/* bpt_helper.c */
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bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update);
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#endif /* I386_HELPER_TCG_H */
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