
There are going to be some potential overheads to CXL enablement, for example the host bridge region reserved in memory maps. Add a machine level control so that CXL is disabled by default. Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220429144110.25167-14-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
25 lines
421 B
C
25 lines
421 B
C
/*
|
|
* QEMU CXL Support
|
|
*
|
|
* Copyright (c) 2020 Intel
|
|
*
|
|
* This work is licensed under the terms of the GNU GPL, version 2. See the
|
|
* COPYING file in the top-level directory.
|
|
*/
|
|
|
|
#ifndef CXL_H
|
|
#define CXL_H
|
|
|
|
#include "cxl_pci.h"
|
|
#include "cxl_component.h"
|
|
#include "cxl_device.h"
|
|
|
|
#define CXL_COMPONENT_REG_BAR_IDX 0
|
|
#define CXL_DEVICE_REG_BAR_IDX 2
|
|
|
|
typedef struct CXLState {
|
|
bool is_enabled;
|
|
} CXLState;
|
|
|
|
#endif
|