c696e1f2b3
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible controller. The SDHCI compatible registers start from offset 0x200, which are called Slot Register Set (SRS) in its datasheet. This creates a Cadence SDHCI model built on top of the existing generic SDHCI model. Cadence specific Host Register Set (HRS) is implemented to make guest software happy. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
26 lines
290 B
Plaintext
26 lines
290 B
Plaintext
config PL181
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bool
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select SD
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config SSI_SD
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bool
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depends on SSI
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select SD
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config SD
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bool
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config SDHCI
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bool
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select SD
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config SDHCI_PCI
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bool
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default y if PCI_DEVICES
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depends on PCI
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select SDHCI
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config CADENCE_SDHCI
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bool
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select SDHCI
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