qemu/target/mips
Aleksandar Markovic ab8c34105a target/mips: Add missing 'break' for a case of MTHC0 handling
This was found by GCC 8.3 static analysis.

Fixes: 5fb2dcd179

Reported-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1563220847-14630-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-07-15 22:21:56 +02:00
..
cp0_timer.c
cpu-param.h
cpu-qom.h
cpu.c
cpu.h
dsp_helper.c
gdbstub.c
helper.c
helper.h
internal.h
kvm_mips.h
kvm.c
lmi_helper.c
machine.c
Makefile.objs
mips-defs.h
mips-semi.c
msa_helper.c
op_helper.c
TODO
trace-events
translate_init.inc.c
translate.c target/mips: Add missing 'break' for a case of MTHC0 handling 2019-07-15 22:21:56 +02:00