31e3f318c8
They are duplicate of running throttling timer flags and incomplete as the flags are not cleared when the interrupts are fired or the device is reset. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
157 lines
3.9 KiB
C
157 lines
3.9 KiB
C
/*
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* Core code for QEMU e1000e emulation
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*
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* Software developer's manuals:
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* http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
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*
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* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
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* Developed by Daynix Computing LTD (http://www.daynix.com)
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*
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* Authors:
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* Dmitry Fleytman <dmitry@daynix.com>
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* Leonid Bloch <leonid@daynix.com>
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* Yan Vugenfirer <yan@daynix.com>
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*
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* Based on work done by:
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* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
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* Copyright (c) 2008 Qumranet
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* Based on work done by:
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* Copyright (c) 2007 Dan Aloni
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* Copyright (c) 2004 Antony T Curtis
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_NET_E1000E_CORE_H
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#define HW_NET_E1000E_CORE_H
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#define E1000E_PHY_PAGE_SIZE (0x20)
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#define E1000E_PHY_PAGES (0x07)
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#define E1000E_MAC_SIZE (0x8000)
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#define E1000E_EEPROM_SIZE (64)
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#define E1000E_MSIX_VEC_NUM (5)
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#define E1000E_NUM_QUEUES (2)
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typedef struct E1000Core E1000ECore;
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enum { PHY_R = BIT(0),
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PHY_W = BIT(1),
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PHY_RW = PHY_R | PHY_W,
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PHY_ANYPAGE = BIT(2) };
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typedef struct E1000IntrDelayTimer_st {
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QEMUTimer *timer;
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bool running;
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uint32_t delay_reg;
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uint32_t delay_resolution_ns;
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E1000ECore *core;
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} E1000IntrDelayTimer;
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struct E1000Core {
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uint32_t mac[E1000E_MAC_SIZE];
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uint16_t phy[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE];
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uint16_t eeprom[E1000E_EEPROM_SIZE];
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uint32_t rxbuf_sizes[E1000_PSRCTL_BUFFS_PER_DESC];
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uint32_t rx_desc_buf_size;
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uint32_t rxbuf_min_shift;
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uint8_t rx_desc_len;
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QEMUTimer *autoneg_timer;
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struct e1000e_tx {
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e1000x_txd_props props;
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bool skip_cp;
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unsigned char sum_needed;
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bool cptse;
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struct NetTxPkt *tx_pkt;
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} tx[E1000E_NUM_QUEUES];
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struct NetRxPkt *rx_pkt;
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bool has_vnet;
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int max_queue_num;
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/* Interrupt moderation management */
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uint32_t delayed_causes;
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E1000IntrDelayTimer radv;
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E1000IntrDelayTimer rdtr;
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E1000IntrDelayTimer raid;
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E1000IntrDelayTimer tadv;
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E1000IntrDelayTimer tidv;
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E1000IntrDelayTimer itr;
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E1000IntrDelayTimer eitr[E1000E_MSIX_VEC_NUM];
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VMChangeStateEntry *vmstate;
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uint32_t itr_guest_value;
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uint32_t eitr_guest_value[E1000E_MSIX_VEC_NUM];
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uint16_t vet;
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uint8_t permanent_mac[ETH_ALEN];
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NICState *owner_nic;
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PCIDevice *owner;
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void (*owner_start_recv)(PCIDevice *d);
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uint32_t msi_causes_pending;
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};
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void
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e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size);
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uint64_t
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e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size);
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void
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e1000e_core_pci_realize(E1000ECore *regs,
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const uint16_t *eeprom_templ,
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uint32_t eeprom_size,
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const uint8_t *macaddr);
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void
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e1000e_core_reset(E1000ECore *core);
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void
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e1000e_core_pre_save(E1000ECore *core);
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int
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e1000e_core_post_load(E1000ECore *core);
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void
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e1000e_core_set_link_status(E1000ECore *core);
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void
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e1000e_core_pci_uninit(E1000ECore *core);
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bool
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e1000e_can_receive(E1000ECore *core);
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ssize_t
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e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size);
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ssize_t
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e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt);
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void
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e1000e_start_recv(E1000ECore *core);
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#endif
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