eb19d9079e
These memops perform interleave decoding, walking down the CXL topology from CFMWS described host interleave decoder via CXL host bridge HDM decoders, through the CXL root ports and finally call CXL type 3 specific read and write functions. Note that, whilst functional the current implementation does not support: * switches * multiple HDM decoders at a given level. * unaligned accesses across the interleave boundaries Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-Id: <20220429144110.25167-34-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
17 lines
432 B
C
17 lines
432 B
C
/*
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* CXL host parameter parsing routine stubs
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*
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* Copyright (c) 2022 Huawei
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/cxl/cxl.h"
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void cxl_fixed_memory_window_config(MachineState *ms,
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CXLFixedMemoryWindowOptions *object,
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Error **errp) {};
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void cxl_fixed_memory_window_link_targets(Error **errp) {};
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const MemoryRegionOps cfmws_ops;
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