qemu/target/arm
Peter Maydell aa1b3111b3 target-arm: Expose output GPIO line for VCPU maintenance interrupt
The GICv3 support for virtualization includes an outbound
maintenance interrupt signal which is asserted when the
CPU interface wants to signal to the hypervisor that it
needs attention. Expose this as an outbound GPIO line from
the CPU object which can be wired up as a physical interrupt
line by the board code (as we do already for the CPU timers).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 1483977924-14522-4-git-send-email-peter.maydell@linaro.org
2017-01-20 11:15:09 +00:00
..
arch_dump.c
arm_ldst.h
arm-powerctl.c
arm-powerctl.h
arm-semi.c
cpu64.c
cpu-qom.h
cpu.c target-arm: Expose output GPIO line for VCPU maintenance interrupt 2017-01-20 11:15:09 +00:00
cpu.h target-arm: Expose output GPIO line for VCPU maintenance interrupt 2017-01-20 11:15:09 +00:00
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c target-arm: Use clrsb helper 2017-01-10 08:47:48 -08:00
helper-a64.h target-arm: Use clrsb helper 2017-01-10 08:47:48 -08:00
helper.c target/arm: Implement DBGVCR32_EL2 system register 2017-01-20 11:15:07 +00:00
helper.h target-arm: Use clz opcode 2017-01-10 08:06:11 -08:00
internals.h
iwmmxt_helper.c
kvm32.c
kvm64.c
kvm_arm.h
kvm-consts.h
kvm-stub.c
kvm.c
machine.c
Makefile.objs
monitor.c
neon_helper.c
op_addsub.h
op_helper.c target-arm: Log AArch64 exception returns 2016-12-27 14:59:25 +00:00
psci.c
trace-events
translate-a64.c target/arm: Fix ubfx et al for aarch64 2017-01-13 09:48:20 -08:00
translate.c target-arm: Use clz opcode 2017-01-10 08:06:11 -08:00
translate.h