Richard Henderson a974879b45 target/riscv: Reorg csr instructions ... Introduce csrr and csrw helpers, for read-only and write-only insns. Note that we do not properly implement this in riscv_csrrw, in that we cannot distinguish true read-only (rs1 == 0) from any other zero write_mask another source register -- this should still raise an exception for read-only registers. Only issue gen_io_start for CF_USE_ICOUNT. Use ctx->zero for csrrc. Use get_gpr and dest_gpr. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-19-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-09-01 11:59:12 +10:00
..
trans_privileged.c.inc	riscv: Add semihosting support	2021-01-18 10:05:06 +00:00
trans_rva.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00
trans_rvb.c.inc	target/riscv: Use DisasExtend in shift operations	2021-09-01 11:59:12 +10:00
trans_rvd.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00
trans_rvf.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00
trans_rvh.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00
trans_rvi.c.inc	target/riscv: Reorg csr instructions	2021-09-01 11:59:12 +10:00
trans_rvm.c.inc	target/riscv: Move gen_* helpers for RVM	2021-09-01 11:59:12 +10:00
trans_rvv.c.inc	target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr	2021-09-01 11:59:12 +10:00