a96edb687e
FEAT_WFxT introduces new instructions WFIT and WFET, which are like the existing WFI and WFE but allow the guest to pass a timeout value in a register. The instructions will wait for an interrupt/event as usual, but will also stop waiting when the value of CNTVCT_EL0 is greater than or equal to the specified timeout value. We implement WFIT by setting up a timer to expire at the right point; when the timer expires it sets the EXITTB interrupt, which will cause the CPU to leave the halted state. If we come out of halt for some other reason, we unset the pending timer. We implement WFET as a nop, which is architecturally permitted and matches the way we currently make WFE a nop. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240430140035.3889879-3-peter.maydell@linaro.org
194 lines
8.8 KiB
ReStructuredText
194 lines
8.8 KiB
ReStructuredText
.. _Arm Emulation:
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A-profile CPU architecture support
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==================================
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QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and
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Armv8 versions of the A-profile architecture. It also has support for
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the following architecture extensions:
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- FEAT_AA32BF16 (AArch32 BFloat16 instructions)
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- FEAT_AA32EL0 (Support for AArch32 at EL0)
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- FEAT_AA32EL1 (Support for AArch32 at EL1)
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- FEAT_AA32EL2 (Support for AArch32 at EL2)
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- FEAT_AA32EL3 (Support for AArch32 at EL3)
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- FEAT_AA32HPD (AArch32 hierarchical permission disables)
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- FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
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- FEAT_AA64EL0 (Support for AArch64 at EL0)
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- FEAT_AA64EL1 (Support for AArch64 at EL1)
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- FEAT_AA64EL2 (Support for AArch64 at EL2)
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- FEAT_AA64EL3 (Support for AArch64 at EL3)
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- FEAT_AdvSIMD (Advanced SIMD Extension)
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- FEAT_AES (AESD and AESE instructions)
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- FEAT_Armv9_Crypto (Armv9 Cryptographic Extension)
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- FEAT_ASID16 (16 bit ASID)
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- FEAT_BBM at level 2 (Translation table break-before-make levels)
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- FEAT_BF16 (AArch64 BFloat16 instructions)
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- FEAT_BTI (Branch Target Identification)
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- FEAT_CCIDX (Extended cache index)
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- FEAT_CRC32 (CRC32 instructions)
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- FEAT_Crypto (Cryptographic Extension)
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- FEAT_CSV2 (Cache speculation variant 2)
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- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
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- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
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- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
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- FEAT_CSV2_3 (Cache speculation variant 2, version 3)
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- FEAT_CSV3 (Cache speculation variant 3)
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- FEAT_DGH (Data gathering hint)
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- FEAT_DIT (Data Independent Timing instructions)
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- FEAT_DPB (DC CVAP instruction)
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- FEAT_DPB2 (DC CVADP instruction)
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- FEAT_Debugv8p1 (Debug with VHE)
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- FEAT_Debugv8p2 (Debug changes for v8.2)
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- FEAT_Debugv8p4 (Debug changes for v8.4)
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- FEAT_DotProd (Advanced SIMD dot product instructions)
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- FEAT_DoubleFault (Double Fault Extension)
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- FEAT_E0PD (Preventing EL0 access to halves of address maps)
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- FEAT_ECV (Enhanced Counter Virtualization)
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- FEAT_EL0 (Support for execution at EL0)
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- FEAT_EL1 (Support for execution at EL1)
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- FEAT_EL2 (Support for execution at EL2)
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- FEAT_EL3 (Support for execution at EL3)
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- FEAT_EPAC (Enhanced pointer authentication)
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- FEAT_ETS2 (Enhanced Translation Synchronization)
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- FEAT_EVT (Enhanced Virtualization Traps)
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- FEAT_F32MM (Single-precision Matrix Multiplication)
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- FEAT_F64MM (Double-precision Matrix Multiplication)
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- FEAT_FCMA (Floating-point complex number instructions)
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- FEAT_FGT (Fine-Grained Traps)
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- FEAT_FHM (Floating-point half-precision multiplication instructions)
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- FEAT_FP (Floating Point extensions)
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- FEAT_FP16 (Half-precision floating-point data processing)
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- FEAT_FPAC (Faulting on AUT* instructions)
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- FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
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- FEAT_FPACC_SPEC (Speculative behavior of combined pointer authentication instructions)
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- FEAT_FRINTTS (Floating-point to integer instructions)
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- FEAT_FlagM (Flag manipulation instructions v2)
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- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
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- FEAT_GTG (Guest translation granule size)
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- FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
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- FEAT_HBC (Hinted conditional branches)
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- FEAT_HCX (Support for the HCRX_EL2 register)
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- FEAT_HPDS (Hierarchical permission disables)
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- FEAT_HPDS2 (Translation table page-based hardware attributes)
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- FEAT_HPMN0 (Setting of MDCR_EL2.HPMN to zero)
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- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
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- FEAT_IDST (ID space trap handling)
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- FEAT_IESB (Implicit error synchronization event)
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- FEAT_JSCVT (JavaScript conversion instructions)
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- FEAT_LOR (Limited ordering regions)
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- FEAT_LPA (Large Physical Address space)
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- FEAT_LPA2 (Large Physical and virtual Address space v2)
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- FEAT_LRCPC (Load-acquire RCpc instructions)
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- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
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- FEAT_LSE (Large System Extensions)
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- FEAT_LSE2 (Large System Extensions v2)
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- FEAT_LVA (Large Virtual Address space)
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- FEAT_MixedEnd (Mixed-endian support)
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- FEAT_MixdEndEL0 (Mixed-endian support at EL0)
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- FEAT_MOPS (Standardization of memory operations)
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- FEAT_MTE (Memory Tagging Extension)
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- FEAT_MTE2 (Memory Tagging Extension)
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- FEAT_MTE3 (MTE Asymmetric Fault Handling)
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- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
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- FEAT_NMI (Non-maskable Interrupt)
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- FEAT_NV (Nested Virtualization)
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- FEAT_NV2 (Enhanced nested virtualization support)
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- FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm)
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- FEAT_PACQARMA3 (Pointer authentication - QARMA3 algorithm)
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- FEAT_PACQARMA5 (Pointer authentication - QARMA5 algorithm)
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- FEAT_PAN (Privileged access never)
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- FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)
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- FEAT_PAN3 (Support for SCTLR_ELx.EPAN)
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- FEAT_PAuth (Pointer authentication)
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- FEAT_PAuth2 (Enhancements to pointer authentication)
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- FEAT_PMULL (PMULL, PMULL2 instructions)
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- FEAT_PMUv3 (PMU extension version 3)
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- FEAT_PMUv3p1 (PMU Extensions v3.1)
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- FEAT_PMUv3p4 (PMU Extensions v3.4)
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- FEAT_PMUv3p5 (PMU Extensions v3.5)
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- FEAT_RAS (Reliability, availability, and serviceability)
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- FEAT_RASv1p1 (RAS Extension v1.1)
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- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
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- FEAT_RME (Realm Management Extension) (NB: support status in QEMU is experimental)
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- FEAT_RNG (Random number generator)
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- FEAT_S2FWB (Stage 2 forced Write-Back)
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- FEAT_SB (Speculation Barrier)
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- FEAT_SEL2 (Secure EL2)
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- FEAT_SHA1 (SHA1 instructions)
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- FEAT_SHA256 (SHA256 instructions)
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- FEAT_SHA3 (Advanced SIMD SHA3 instructions)
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- FEAT_SHA512 (Advanced SIMD SHA512 instructions)
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- FEAT_SM3 (Advanced SIMD SM3 instructions)
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- FEAT_SM4 (Advanced SIMD SM4 instructions)
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- FEAT_SME (Scalable Matrix Extension)
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- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
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- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
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- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
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- FEAT_SVE (Scalable Vector Extension)
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- FEAT_SVE_AES (Scalable Vector AES instructions)
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- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions)
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- FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions)
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- FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions)
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- FEAT_SVE_SM4 (Scalable Vector SM4 instructions)
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- FEAT_SVE2 (Scalable Vector Extension version 2)
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- FEAT_SPECRES (Speculation restriction instructions)
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- FEAT_SSBS (Speculative Store Bypass Safe)
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- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
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- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
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- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
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- FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality)
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- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
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- FEAT_TLBIRANGE (TLB invalidate range instructions)
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- FEAT_TTCNP (Translation table Common not private translations)
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- FEAT_TTL (Translation Table Level)
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- FEAT_TTST (Small translation tables)
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- FEAT_UAO (Unprivileged Access Override control)
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- FEAT_VHE (Virtualization Host Extensions)
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- FEAT_VMID16 (16-bit VMID)
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- FEAT_WFxT (WFE and WFI instructions with timeout)
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- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
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For information on the specifics of these extensions, please refer
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to the `Armv8-A Arm Architecture Reference Manual
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<https://developer.arm.com/documentation/ddi0487/latest>`_.
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When a specific named CPU is being emulated, only those features which
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are present in hardware for that CPU are emulated. (If a feature is
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not in the list above then it is not supported, even if the real
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hardware should have it.) The ``max`` CPU enables all features.
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R-profile CPU architecture support
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==================================
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QEMU's TCG emulation support for R-profile CPUs is currently limited.
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We emulate only the Cortex-R5 and Cortex-R5F CPUs.
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M-profile CPU architecture support
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==================================
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QEMU's TCG emulation includes support for Armv6-M, Armv7-M, Armv8-M, and
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Armv8.1-M versions of the M-profile architucture. It also has support
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for the following architecture extensions:
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- FP (Floating-point Extension)
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- FPCXT (FPCXT access instructions)
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- HP (Half-precision floating-point instructions)
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- LOB (Low Overhead loops and Branch future)
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- M (Main Extension)
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- MPU (Memory Protection Unit Extension)
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- PXN (Privileged Execute Never)
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- RAS (Reliability, Serviceability and Availability): "minimum RAS Extension" only
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- S (Security Extension)
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- ST (System Timer Extension)
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For information on the specifics of these extensions, please refer
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to the `Armv8-M Arm Architecture Reference Manual
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<https://developer.arm.com/documentation/ddi0553/latest>`_.
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When a specific named CPU is being emulated, only those features which
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are present in hardware for that CPU are emulated. (If a feature is
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not in the list above then it is not supported, even if the real
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hardware should have it.) There is no equivalent of the ``max`` CPU for
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M-profile.
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