Rob Herring f72dbf3d26 pl011: fix incorrect logic to set the RXFF flag ...

The receive fifo full bit should be set when 1 character is received and
the fifo is disabled or when 16 characters are in the fifo.

Signed-off-by: Rob Herring <rob.herring@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1395166721-15716-4-git-send-email-robherring2@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2014-03-18 19:38:56 +00:00

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cadence_uart.c

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debugcon.c

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digic-uart.c

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escc.c

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etraxfs_ser.c

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exynos4210_uart.c

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grlib_apbuart.c

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imx_serial.c

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ipoctal232.c

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lm32_juart.c

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lm32_uart.c

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Makefile.objs

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mcf_uart.c

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milkymist-uart.c

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omap_uart.c

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parallel.c

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pl011.c

pl011: fix incorrect logic to set the RXFF flag

2014-03-18 19:38:56 +00:00

sclpconsole-lm.c

s390x/sclpconsole-lm: Fix and simplify irq setup

2014-03-17 22:01:19 +01:00

sclpconsole.c

s390x/sclpconsole: Fix and simplify interrupt injection

2014-03-17 22:01:19 +01:00

serial-isa.c

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serial-pci.c

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serial.c

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sh_serial.c

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spapr_vty.c

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virtio-console.c

virtio-console: Fix VIRTIO_CONSOLE() cast macro

2014-03-13 21:12:07 +01:00

virtio-serial-bus.c

virtio-serial-port: Convert to QOM realize/unrealize

2014-03-13 01:21:57 +01:00

xen_console.c

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xilinx_uartlite.c

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