qemu/hw/i2c
Jamin Lin be8c15118a hw/i2c/aspeed: Add support for 64 bit addresses
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
and the base address of dram is "0x4 00000000" which
is 64bits address.

The AST2700 support the maximum DRAM size is 8 GB.
The DRAM physical address range is from "0x4_0000_0000" to
"0x5_FFFF_FFFF".

The DRAM offset range is from "0x0_0000_0000" to
"0x1_FFFF_FFFF" and it is enough to use bits [33:0]
saving the dram offset.

Therefore, save the high part physical address bit[1:0]
of Tx/Rx buffer address as dma_dram_offset bit[33:32].
It does not need to decrease the dram physical
high part address for DMA operation.
(high part physical address bit[7:0] – 4)

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-09-16 17:44:08 +02:00
..
allwinner-i2c.c
arm_sbcon_i2c.c
aspeed_i2c.c
bcm2835_i2c.c
bitbang_i2c.c
core.c
exynos4210_i2c.c
i2c_mux_pca954x.c
imx_i2c.c
Kconfig
meson.build
microbit_i2c.c
mpc_i2c.c
npcm7xx_smbus.c
omap_i2c.c
pm_smbus.c
pmbus_device.c
ppc4xx_i2c.c
smbus_eeprom.c
smbus_ich9.c
smbus_master.c
smbus_slave.c
trace-events
trace.h