qemu/target-tricore
Bastian Koppelmann 828066c78a target-tricore: add opd trap generation
If an instruction uses a 64 bit register which consists of an even-odd pair
of 32 bit registers and if the register specifier in the instruction is
odd an opd trap is raised.

Reviewed-by: Richard Henderson  <rth@twiddle.net>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <1455889426-1923-5-git-send-email-kbastian@mail.uni-paderborn.de>
2016-02-25 12:54:50 +01:00
..
cpu-qom.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
cpu.c tricore: Clean up includes 2016-01-29 15:07:25 +00:00
cpu.h target-tricore: Add trap handling & SOVF/OVF traps 2016-02-25 12:54:42 +01:00
csfr.def target-tricore: Fix new typos 2015-01-15 10:44:13 +03:00
helper.c target-tricore: Fix wrong precedences on psw_write 2016-02-25 12:51:31 +01:00
helper.h target-tricore: Add trap handling & SOVF/OVF traps 2016-02-25 12:54:42 +01:00
Makefile.objs
op_helper.c target-tricore: add context managment trap generation 2016-02-25 12:54:45 +01:00
translate.c target-tricore: add opd trap generation 2016-02-25 12:54:50 +01:00
tricore-defs.h
tricore-opcodes.h target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA 2015-05-22 17:02:34 +02:00