Richard Henderson a77ca425d7 target/i386: Reduce DisasContext.vex_[lv] to uint8_t ... Currently, vex_l is either {0,1}; if in the future we implement AVX-512, the max value will be 2. In vex_v we store a register number. This is 0-15 for SSE, and 0-31 for AVX-512. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-24-richard.henderson@linaro.org>		2021-05-19 12:15:47 -05:00
..
sysemu	target/i386: use mmu_translate for NPT walk	2021-05-11 04:11:14 -04:00
user	i386: split seg_helper into user-only and sysemu parts	2021-05-10 15:41:52 -04:00
bpt_helper.c	i386: move TCG bpt_helper into sysemu/	2021-05-10 15:41:51 -04:00
cc_helper_template.h
cc_helper.c
excp_helper.c	i386: split tcg excp_helper into sysemu and user parts	2021-05-10 15:41:51 -04:00
fpu_helper.c	i386: separate fpu_helper sysemu-only parts	2021-05-10 15:41:51 -04:00
helper-tcg.h	i386: split seg_helper into user-only and sysemu parts	2021-05-10 15:41:52 -04:00
int_helper.c
mem_helper.c	exec: Use cpu_untagged_addr in g2h; split out g2h_untagged	2021-02-16 11:04:53 +00:00
meson.build	i386: split svm_helper into sysemu and stub-only user	2021-05-10 15:41:51 -04:00
misc_helper.c	i386: split misc helper user stubs and sysemu part	2021-05-10 15:41:51 -04:00
mpx_helper.c
seg_helper.c	i386: split seg_helper into user-only and sysemu parts	2021-05-10 15:41:52 -04:00
seg_helper.h	i386: split seg_helper into user-only and sysemu parts	2021-05-10 15:41:52 -04:00
tcg-cpu.c	accel: add init_accel_cpu for adapting accel behavior to CPU type	2021-05-10 15:41:52 -04:00
tcg-cpu.h	i386: split off sysemu-only functionality in tcg-cpu	2021-05-10 15:41:50 -04:00
tcg-stub.c
translate.c	target/i386: Reduce DisasContext.vex_[lv] to uint8_t	2021-05-19 12:15:47 -05:00