qemu/target/riscv/insn_trans
Frank Chang a69f97c111 target/riscv: fix return value of do_opivx_widen()
do_opivx_widen() should return false if check function returns false.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200710104920.13550-4-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-07-13 17:25:37 -07:00
..
trans_privileged.inc.c target/riscv: Move the hfence instructions to the rvh decode 2020-06-19 08:24:07 -07:00
trans_rva.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
trans_rvd.inc.c target/riscv: fsd/fsw doesn't dirty FP state 2020-01-16 10:03:08 -08:00
trans_rvf.inc.c riscv: Add helper to make NaN-boxing for FP register 2020-06-19 08:24:07 -07:00
trans_rvh.inc.c target/riscv: Implement checks for hfence 2020-06-19 08:24:07 -07:00
trans_rvi.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
trans_rvm.inc.c target/riscv: Zero extend the inputs of divuw and remuw 2019-03-22 00:26:39 -07:00
trans_rvv.inc.c target/riscv: fix return value of do_opivx_widen() 2020-07-13 17:25:37 -07:00