Bin Meng 9eb8b14a70 hw/riscv: Modify MROM size to end at 0x10000 ...

At present the size of Mask ROM for sifive_u / spike / virt machines
is set to 0x11000, which ends at an unusual address. This changes the
size to 0xf000 so that it ends at 0x10000.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1594289144-24723-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2020-07-13 17:25:37 -07:00

..

boot.c

RISC-V: Support 64 bit start address

2020-07-13 17:25:37 -07:00

Kconfig

hw/char: Initial commit of Ibex UART

2020-06-19 08:24:07 -07:00

Makefile.objs

…

opentitan.c

error: Eliminate error_propagate() with Coccinelle, part 1

2020-07-10 15:18:08 +02:00

riscv_hart.c

riscv_hart: Fix riscv_harts_realize() error API violations

2020-07-02 06:25:29 +02:00

riscv_htif.c

…

sifive_clint.c

hw/riscv: Allow 64 bit access to SiFive CLINT

2020-07-02 09:19:32 -07:00

sifive_e_prci.c

sysbus: Convert to sysbus_realize() etc. with Coccinelle

2020-06-15 22:05:28 +02:00

sifive_e.c

error: Eliminate error_propagate() with Coccinelle, part 1

2020-07-10 15:18:08 +02:00

sifive_gpio.c

hw/riscv: sifive_gpio: Do not blindly trigger output IRQs

2020-06-19 08:25:27 -07:00

sifive_plic.c

riscv: plic: Add a couple of mising sifive_plic_update calls

2020-07-02 09:19:32 -07:00

sifive_test.c

sysbus: Convert to sysbus_realize() etc. with Coccinelle

2020-06-15 22:05:28 +02:00

sifive_u_otp.c

…

sifive_u_prci.c

…

sifive_u.c

hw/riscv: Modify MROM size to end at 0x10000

2020-07-13 17:25:37 -07:00

sifive_uart.c

…

spike.c

hw/riscv: Modify MROM size to end at 0x10000

2020-07-13 17:25:37 -07:00

trace-events

…

virt.c

hw/riscv: Modify MROM size to end at 0x10000

2020-07-13 17:25:37 -07:00