9988c7b50e
TILE-Gx has been removed during the v6.0 release (see
commit 2cc1a90166 "Remove deprecated target tilegx"),
no need to mention it in the list of "supported targets".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
861 lines
29 KiB
C++
861 lines
29 KiB
C++
/*
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* QEMU float support
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*
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* The code in this source file is derived from release 2a of the SoftFloat
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* IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
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* some later contributions) are provided under that license, as detailed below.
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* It has subsequently been modified by contributors to the QEMU Project,
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* so some portions are provided under:
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* the SoftFloat-2a license
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* the BSD license
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* GPL-v2-or-later
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*
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* Any future contributions to this file after December 1st 2014 will be
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* taken to be licensed under the Softfloat-2a license unless specifically
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* indicated otherwise.
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*/
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/*
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===============================================================================
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This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
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Arithmetic Package, Release 2a.
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Written by John R. Hauser. This work was made possible in part by the
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International Computer Science Institute, located at Suite 600, 1947 Center
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Street, Berkeley, California 94704. Funding was partially provided by the
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National Science Foundation under grant MIP-9311980. The original version
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of this code was written as part of a project to build a fixed-point vector
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processor in collaboration with the University of California at Berkeley,
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overseen by Profs. Nelson Morgan and John Wawrzynek. More information
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is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
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arithmetic/SoftFloat.html'.
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THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
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has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
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TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
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PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
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AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
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Derivative works are acceptable, even for commercial purposes, so long as
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(1) they include prominent notice that the work is derivative, and (2) they
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include prominent notice akin to these four paragraphs for those parts of
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this code that are retained.
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===============================================================================
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*/
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/* BSD licensing:
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* Copyright (c) 2006, Fabrice Bellard
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Portions of this work are licensed under the terms of the GNU GPL,
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* version 2 or later. See the COPYING file in the top-level directory.
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*/
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/*
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* Define whether architecture deviates from IEEE in not supporting
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* signaling NaNs (so all NaNs are treated as quiet).
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*/
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static inline bool no_signaling_nans(float_status *status)
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{
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#if defined(TARGET_XTENSA)
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return status->no_signaling_nans;
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#else
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return false;
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#endif
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}
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/* Define how the architecture discriminates signaling NaNs.
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* This done with the most significant bit of the fraction.
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* In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
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* the msb must be zero. MIPS is (so far) unique in supporting both the
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* 2008 revision and backward compatibility with their original choice.
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* Thus for MIPS we must make the choice at runtime.
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*/
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static inline bool snan_bit_is_one(float_status *status)
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{
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#if defined(TARGET_MIPS)
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return status->snan_bit_is_one;
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#elif defined(TARGET_HPPA) || defined(TARGET_SH4)
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return 1;
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#else
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return 0;
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#endif
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}
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/*----------------------------------------------------------------------------
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| For the deconstructed floating-point with fraction FRAC, return true
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| if the fraction represents a signalling NaN; otherwise false.
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*----------------------------------------------------------------------------*/
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static bool parts_is_snan_frac(uint64_t frac, float_status *status)
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{
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if (no_signaling_nans(status)) {
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return false;
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} else {
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bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
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return msb == snan_bit_is_one(status);
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}
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}
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/*----------------------------------------------------------------------------
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| The pattern for a default generated deconstructed floating-point NaN.
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*----------------------------------------------------------------------------*/
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static void parts64_default_nan(FloatParts64 *p, float_status *status)
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{
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bool sign = 0;
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uint64_t frac;
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#if defined(TARGET_SPARC) || defined(TARGET_M68K)
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/* !snan_bit_is_one, set all bits */
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frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
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#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
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|| defined(TARGET_MICROBLAZE)
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/* !snan_bit_is_one, set sign and msb */
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frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
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sign = 1;
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#elif defined(TARGET_HPPA)
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/* snan_bit_is_one, set msb-1. */
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frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
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#elif defined(TARGET_HEXAGON)
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sign = 1;
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frac = ~0ULL;
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#else
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/*
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* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
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* S390, SH4, TriCore, and Xtensa. Our other supported targets,
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* CRIS and Nios2, do not have floating-point.
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*/
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if (snan_bit_is_one(status)) {
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/* set all bits other than msb */
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frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
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} else {
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/* set msb */
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frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
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}
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#endif
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*p = (FloatParts64) {
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.cls = float_class_qnan,
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.sign = sign,
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.exp = INT_MAX,
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.frac = frac
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};
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}
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static void parts128_default_nan(FloatParts128 *p, float_status *status)
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{
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/*
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* Extrapolate from the choices made by parts64_default_nan to fill
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* in the quad-floating format. If the low bit is set, assume we
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* want to set all non-snan bits.
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*/
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FloatParts64 p64;
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parts64_default_nan(&p64, status);
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*p = (FloatParts128) {
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.cls = float_class_qnan,
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.sign = p64.sign,
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.exp = INT_MAX,
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.frac_hi = p64.frac,
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.frac_lo = -(p64.frac & 1)
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};
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}
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/*----------------------------------------------------------------------------
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| Returns a quiet NaN from a signalling NaN for the deconstructed
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| floating-point parts.
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*----------------------------------------------------------------------------*/
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static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status)
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{
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g_assert(!no_signaling_nans(status));
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/* The only snan_bit_is_one target without default_nan_mode is HPPA. */
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if (snan_bit_is_one(status)) {
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frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));
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frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);
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} else {
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frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);
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}
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return frac;
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}
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static void parts64_silence_nan(FloatParts64 *p, float_status *status)
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{
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p->frac = parts_silence_nan_frac(p->frac, status);
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p->cls = float_class_qnan;
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}
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static void parts128_silence_nan(FloatParts128 *p, float_status *status)
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{
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p->frac_hi = parts_silence_nan_frac(p->frac_hi, status);
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p->cls = float_class_qnan;
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}
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/*----------------------------------------------------------------------------
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| The pattern for a default generated extended double-precision NaN.
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*----------------------------------------------------------------------------*/
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floatx80 floatx80_default_nan(float_status *status)
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{
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floatx80 r;
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/* None of the targets that have snan_bit_is_one use floatx80. */
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assert(!snan_bit_is_one(status));
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#if defined(TARGET_M68K)
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r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
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r.high = 0x7FFF;
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#else
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/* X86 */
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r.low = UINT64_C(0xC000000000000000);
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r.high = 0xFFFF;
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#endif
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return r;
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}
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/*----------------------------------------------------------------------------
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| The pattern for a default generated extended double-precision inf.
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*----------------------------------------------------------------------------*/
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#define floatx80_infinity_high 0x7FFF
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#if defined(TARGET_M68K)
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#define floatx80_infinity_low UINT64_C(0x0000000000000000)
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#else
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#define floatx80_infinity_low UINT64_C(0x8000000000000000)
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#endif
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const floatx80 floatx80_infinity
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= make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
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/*----------------------------------------------------------------------------
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| Returns 1 if the half-precision floating-point value `a' is a quiet
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| NaN; otherwise returns 0.
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*----------------------------------------------------------------------------*/
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bool float16_is_quiet_nan(float16 a_, float_status *status)
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{
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if (no_signaling_nans(status)) {
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return float16_is_any_nan(a_);
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} else {
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uint16_t a = float16_val(a_);
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if (snan_bit_is_one(status)) {
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return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
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} else {
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return ((a >> 9) & 0x3F) == 0x3F;
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}
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}
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}
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/*----------------------------------------------------------------------------
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| Returns 1 if the bfloat16 value `a' is a quiet
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| NaN; otherwise returns 0.
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*----------------------------------------------------------------------------*/
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bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status)
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{
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if (no_signaling_nans(status)) {
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return bfloat16_is_any_nan(a_);
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} else {
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uint16_t a = a_;
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if (snan_bit_is_one(status)) {
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return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
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} else {
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return ((a >> 6) & 0x1FF) == 0x1FF;
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}
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}
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}
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/*----------------------------------------------------------------------------
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| Returns 1 if the half-precision floating-point value `a' is a signaling
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| NaN; otherwise returns 0.
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*----------------------------------------------------------------------------*/
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bool float16_is_signaling_nan(float16 a_, float_status *status)
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{
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if (no_signaling_nans(status)) {
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return 0;
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} else {
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uint16_t a = float16_val(a_);
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if (snan_bit_is_one(status)) {
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return ((a >> 9) & 0x3F) == 0x3F;
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} else {
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return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
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}
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}
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}
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/*----------------------------------------------------------------------------
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| Returns 1 if the bfloat16 value `a' is a signaling
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| NaN; otherwise returns 0.
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*----------------------------------------------------------------------------*/
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bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status)
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{
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if (no_signaling_nans(status)) {
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return 0;
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} else {
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uint16_t a = a_;
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if (snan_bit_is_one(status)) {
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return ((a >> 6) & 0x1FF) == 0x1FF;
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} else {
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return (((a >> 6) & 0x1FF) == 0x1FE) && (a & 0x3F);
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}
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}
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}
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/*----------------------------------------------------------------------------
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| Returns 1 if the single-precision floating-point value `a' is a quiet
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| NaN; otherwise returns 0.
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*----------------------------------------------------------------------------*/
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bool float32_is_quiet_nan(float32 a_, float_status *status)
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{
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if (no_signaling_nans(status)) {
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return float32_is_any_nan(a_);
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} else {
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uint32_t a = float32_val(a_);
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if (snan_bit_is_one(status)) {
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return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
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} else {
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return ((uint32_t)(a << 1) >= 0xFF800000);
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}
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}
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}
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/*----------------------------------------------------------------------------
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| Returns 1 if the single-precision floating-point value `a' is a signaling
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| NaN; otherwise returns 0.
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*----------------------------------------------------------------------------*/
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bool float32_is_signaling_nan(float32 a_, float_status *status)
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{
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if (no_signaling_nans(status)) {
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return 0;
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} else {
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uint32_t a = float32_val(a_);
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if (snan_bit_is_one(status)) {
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return ((uint32_t)(a << 1) >= 0xFF800000);
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} else {
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return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
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}
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}
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}
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/*----------------------------------------------------------------------------
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| Select which NaN to propagate for a two-input operation.
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| IEEE754 doesn't specify all the details of this, so the
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| algorithm is target-specific.
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| The routine is passed various bits of information about the
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| two NaNs and should return 0 to select NaN a and 1 for NaN b.
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| Note that signalling NaNs are always squashed to quiet NaNs
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| by the caller, by calling floatXX_silence_nan() before
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| returning them.
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|
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| aIsLargerSignificand is only valid if both a and b are NaNs
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| of some kind, and is true if a has the larger significand,
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| or if both a and b have the same significand but a is
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| positive but b is negative. It is only needed for the x87
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| tie-break rule.
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*----------------------------------------------------------------------------*/
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static int pickNaN(FloatClass a_cls, FloatClass b_cls,
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bool aIsLargerSignificand, float_status *status)
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{
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#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) || \
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defined(TARGET_LOONGARCH64) || defined(TARGET_S390X)
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/* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
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* the first of:
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* 1. A if it is signaling
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* 2. B if it is signaling
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* 3. A (quiet)
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* 4. B (quiet)
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* A signaling NaN is always quietened before returning it.
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*/
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/* According to MIPS specifications, if one of the two operands is
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* a sNaN, a new qNaN has to be generated. This is done in
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* floatXX_silence_nan(). For qNaN inputs the specifications
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* says: "When possible, this QNaN result is one of the operand QNaN
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* values." In practice it seems that most implementations choose
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* the first operand if both operands are qNaN. In short this gives
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* the following rules:
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* 1. A if it is signaling
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* 2. B if it is signaling
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* 3. A (quiet)
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* 4. B (quiet)
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* A signaling NaN is always silenced before returning it.
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*/
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if (is_snan(a_cls)) {
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return 0;
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} else if (is_snan(b_cls)) {
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return 1;
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} else if (is_qnan(a_cls)) {
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return 0;
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} else {
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return 1;
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}
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#elif defined(TARGET_PPC) || defined(TARGET_M68K)
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/* PowerPC propagation rules:
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* 1. A if it sNaN or qNaN
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* 2. B if it sNaN or qNaN
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* A signaling NaN is always silenced before returning it.
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*/
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/* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
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* 3.4 FLOATING-POINT INSTRUCTION DETAILS
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* If either operand, but not both operands, of an operation is a
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* nonsignaling NaN, then that NaN is returned as the result. If both
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* operands are nonsignaling NaNs, then the destination operand
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* nonsignaling NaN is returned as the result.
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* If either operand to an operation is a signaling NaN (SNaN), then the
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* SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
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* is set in the FPCR ENABLE byte, then the exception is taken and the
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* destination is not modified. If the SNaN exception enable bit is not
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* set, setting the SNaN bit in the operand to a one converts the SNaN to
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* a nonsignaling NaN. The operation then continues as described in the
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* preceding paragraph for nonsignaling NaNs.
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*/
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if (is_nan(a_cls)) {
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return 0;
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} else {
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return 1;
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}
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#elif defined(TARGET_XTENSA)
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/*
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* Xtensa has two NaN propagation modes.
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* Which one is active is controlled by float_status::use_first_nan.
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*/
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if (status->use_first_nan) {
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if (is_nan(a_cls)) {
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return 0;
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} else {
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return 1;
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}
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} else {
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if (is_nan(b_cls)) {
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return 1;
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} else {
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return 0;
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}
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}
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#else
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/* This implements x87 NaN propagation rules:
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* SNaN + QNaN => return the QNaN
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* two SNaNs => return the one with the larger significand, silenced
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* two QNaNs => return the one with the larger significand
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* SNaN and a non-NaN => return the SNaN, silenced
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* QNaN and a non-NaN => return the QNaN
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*
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* If we get down to comparing significands and they are the same,
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* return the NaN with the positive sign bit (if any).
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*/
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if (is_snan(a_cls)) {
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if (is_snan(b_cls)) {
|
|
return aIsLargerSignificand ? 0 : 1;
|
|
}
|
|
return is_qnan(b_cls) ? 1 : 0;
|
|
} else if (is_qnan(a_cls)) {
|
|
if (is_snan(b_cls) || !is_qnan(b_cls)) {
|
|
return 0;
|
|
} else {
|
|
return aIsLargerSignificand ? 0 : 1;
|
|
}
|
|
} else {
|
|
return 1;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------
|
|
| Select which NaN to propagate for a three-input operation.
|
|
| For the moment we assume that no CPU needs the 'larger significand'
|
|
| information.
|
|
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
|
|
*----------------------------------------------------------------------------*/
|
|
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
|
|
bool infzero, float_status *status)
|
|
{
|
|
#if defined(TARGET_ARM)
|
|
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
|
|
* the default NaN
|
|
*/
|
|
if (infzero && is_qnan(c_cls)) {
|
|
float_raise(float_flag_invalid | float_flag_invalid_imz, status);
|
|
return 3;
|
|
}
|
|
|
|
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
|
|
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
|
|
*/
|
|
if (is_snan(c_cls)) {
|
|
return 2;
|
|
} else if (is_snan(a_cls)) {
|
|
return 0;
|
|
} else if (is_snan(b_cls)) {
|
|
return 1;
|
|
} else if (is_qnan(c_cls)) {
|
|
return 2;
|
|
} else if (is_qnan(a_cls)) {
|
|
return 0;
|
|
} else {
|
|
return 1;
|
|
}
|
|
#elif defined(TARGET_MIPS)
|
|
if (snan_bit_is_one(status)) {
|
|
/*
|
|
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
|
|
* case sets InvalidOp and returns the default NaN
|
|
*/
|
|
if (infzero) {
|
|
float_raise(float_flag_invalid | float_flag_invalid_imz, status);
|
|
return 3;
|
|
}
|
|
/* Prefer sNaN over qNaN, in the a, b, c order. */
|
|
if (is_snan(a_cls)) {
|
|
return 0;
|
|
} else if (is_snan(b_cls)) {
|
|
return 1;
|
|
} else if (is_snan(c_cls)) {
|
|
return 2;
|
|
} else if (is_qnan(a_cls)) {
|
|
return 0;
|
|
} else if (is_qnan(b_cls)) {
|
|
return 1;
|
|
} else {
|
|
return 2;
|
|
}
|
|
} else {
|
|
/*
|
|
* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
|
|
* case sets InvalidOp and returns the input value 'c'
|
|
*/
|
|
if (infzero) {
|
|
float_raise(float_flag_invalid | float_flag_invalid_imz, status);
|
|
return 2;
|
|
}
|
|
/* Prefer sNaN over qNaN, in the c, a, b order. */
|
|
if (is_snan(c_cls)) {
|
|
return 2;
|
|
} else if (is_snan(a_cls)) {
|
|
return 0;
|
|
} else if (is_snan(b_cls)) {
|
|
return 1;
|
|
} else if (is_qnan(c_cls)) {
|
|
return 2;
|
|
} else if (is_qnan(a_cls)) {
|
|
return 0;
|
|
} else {
|
|
return 1;
|
|
}
|
|
}
|
|
#elif defined(TARGET_LOONGARCH64)
|
|
/*
|
|
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
|
|
* case sets InvalidOp and returns the input value 'c'
|
|
*/
|
|
if (infzero) {
|
|
float_raise(float_flag_invalid | float_flag_invalid_imz, status);
|
|
return 2;
|
|
}
|
|
/* Prefer sNaN over qNaN, in the c, a, b order. */
|
|
if (is_snan(c_cls)) {
|
|
return 2;
|
|
} else if (is_snan(a_cls)) {
|
|
return 0;
|
|
} else if (is_snan(b_cls)) {
|
|
return 1;
|
|
} else if (is_qnan(c_cls)) {
|
|
return 2;
|
|
} else if (is_qnan(a_cls)) {
|
|
return 0;
|
|
} else {
|
|
return 1;
|
|
}
|
|
#elif defined(TARGET_PPC)
|
|
/* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
|
|
* to return an input NaN if we have one (ie c) rather than generating
|
|
* a default NaN
|
|
*/
|
|
if (infzero) {
|
|
float_raise(float_flag_invalid | float_flag_invalid_imz, status);
|
|
return 2;
|
|
}
|
|
|
|
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
|
|
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
|
|
*/
|
|
if (is_nan(a_cls)) {
|
|
return 0;
|
|
} else if (is_nan(c_cls)) {
|
|
return 2;
|
|
} else {
|
|
return 1;
|
|
}
|
|
#elif defined(TARGET_RISCV)
|
|
/* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
|
|
if (infzero) {
|
|
float_raise(float_flag_invalid | float_flag_invalid_imz, status);
|
|
}
|
|
return 3; /* default NaN */
|
|
#elif defined(TARGET_XTENSA)
|
|
/*
|
|
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
|
|
* an input NaN if we have one (ie c).
|
|
*/
|
|
if (infzero) {
|
|
float_raise(float_flag_invalid | float_flag_invalid_imz, status);
|
|
return 2;
|
|
}
|
|
if (status->use_first_nan) {
|
|
if (is_nan(a_cls)) {
|
|
return 0;
|
|
} else if (is_nan(b_cls)) {
|
|
return 1;
|
|
} else {
|
|
return 2;
|
|
}
|
|
} else {
|
|
if (is_nan(c_cls)) {
|
|
return 2;
|
|
} else if (is_nan(b_cls)) {
|
|
return 1;
|
|
} else {
|
|
return 0;
|
|
}
|
|
}
|
|
#else
|
|
/* A default implementation: prefer a to b to c.
|
|
* This is unlikely to actually match any real implementation.
|
|
*/
|
|
if (is_nan(a_cls)) {
|
|
return 0;
|
|
} else if (is_nan(b_cls)) {
|
|
return 1;
|
|
} else {
|
|
return 2;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------
|
|
| Returns 1 if the double-precision floating-point value `a' is a quiet
|
|
| NaN; otherwise returns 0.
|
|
*----------------------------------------------------------------------------*/
|
|
|
|
bool float64_is_quiet_nan(float64 a_, float_status *status)
|
|
{
|
|
if (no_signaling_nans(status)) {
|
|
return float64_is_any_nan(a_);
|
|
} else {
|
|
uint64_t a = float64_val(a_);
|
|
if (snan_bit_is_one(status)) {
|
|
return (((a >> 51) & 0xFFF) == 0xFFE)
|
|
&& (a & 0x0007FFFFFFFFFFFFULL);
|
|
} else {
|
|
return ((a << 1) >= 0xFFF0000000000000ULL);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------
|
|
| Returns 1 if the double-precision floating-point value `a' is a signaling
|
|
| NaN; otherwise returns 0.
|
|
*----------------------------------------------------------------------------*/
|
|
|
|
bool float64_is_signaling_nan(float64 a_, float_status *status)
|
|
{
|
|
if (no_signaling_nans(status)) {
|
|
return 0;
|
|
} else {
|
|
uint64_t a = float64_val(a_);
|
|
if (snan_bit_is_one(status)) {
|
|
return ((a << 1) >= 0xFFF0000000000000ULL);
|
|
} else {
|
|
return (((a >> 51) & 0xFFF) == 0xFFE)
|
|
&& (a & UINT64_C(0x0007FFFFFFFFFFFF));
|
|
}
|
|
}
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------
|
|
| Returns 1 if the extended double-precision floating-point value `a' is a
|
|
| quiet NaN; otherwise returns 0. This slightly differs from the same
|
|
| function for other types as floatx80 has an explicit bit.
|
|
*----------------------------------------------------------------------------*/
|
|
|
|
int floatx80_is_quiet_nan(floatx80 a, float_status *status)
|
|
{
|
|
if (no_signaling_nans(status)) {
|
|
return floatx80_is_any_nan(a);
|
|
} else {
|
|
if (snan_bit_is_one(status)) {
|
|
uint64_t aLow;
|
|
|
|
aLow = a.low & ~0x4000000000000000ULL;
|
|
return ((a.high & 0x7FFF) == 0x7FFF)
|
|
&& (aLow << 1)
|
|
&& (a.low == aLow);
|
|
} else {
|
|
return ((a.high & 0x7FFF) == 0x7FFF)
|
|
&& (UINT64_C(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
|
|
}
|
|
}
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------
|
|
| Returns 1 if the extended double-precision floating-point value `a' is a
|
|
| signaling NaN; otherwise returns 0. This slightly differs from the same
|
|
| function for other types as floatx80 has an explicit bit.
|
|
*----------------------------------------------------------------------------*/
|
|
|
|
int floatx80_is_signaling_nan(floatx80 a, float_status *status)
|
|
{
|
|
if (no_signaling_nans(status)) {
|
|
return 0;
|
|
} else {
|
|
if (snan_bit_is_one(status)) {
|
|
return ((a.high & 0x7FFF) == 0x7FFF)
|
|
&& ((a.low << 1) >= 0x8000000000000000ULL);
|
|
} else {
|
|
uint64_t aLow;
|
|
|
|
aLow = a.low & ~UINT64_C(0x4000000000000000);
|
|
return ((a.high & 0x7FFF) == 0x7FFF)
|
|
&& (uint64_t)(aLow << 1)
|
|
&& (a.low == aLow);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------
|
|
| Returns a quiet NaN from a signalling NaN for the extended double-precision
|
|
| floating point value `a'.
|
|
*----------------------------------------------------------------------------*/
|
|
|
|
floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
|
|
{
|
|
/* None of the targets that have snan_bit_is_one use floatx80. */
|
|
assert(!snan_bit_is_one(status));
|
|
a.low |= UINT64_C(0xC000000000000000);
|
|
return a;
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------
|
|
| Takes two extended double-precision floating-point values `a' and `b', one
|
|
| of which is a NaN, and returns the appropriate NaN result. If either `a' or
|
|
| `b' is a signaling NaN, the invalid exception is raised.
|
|
*----------------------------------------------------------------------------*/
|
|
|
|
floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
|
|
{
|
|
bool aIsLargerSignificand;
|
|
FloatClass a_cls, b_cls;
|
|
|
|
/* This is not complete, but is good enough for pickNaN. */
|
|
a_cls = (!floatx80_is_any_nan(a)
|
|
? float_class_normal
|
|
: floatx80_is_signaling_nan(a, status)
|
|
? float_class_snan
|
|
: float_class_qnan);
|
|
b_cls = (!floatx80_is_any_nan(b)
|
|
? float_class_normal
|
|
: floatx80_is_signaling_nan(b, status)
|
|
? float_class_snan
|
|
: float_class_qnan);
|
|
|
|
if (is_snan(a_cls) || is_snan(b_cls)) {
|
|
float_raise(float_flag_invalid, status);
|
|
}
|
|
|
|
if (status->default_nan_mode) {
|
|
return floatx80_default_nan(status);
|
|
}
|
|
|
|
if (a.low < b.low) {
|
|
aIsLargerSignificand = 0;
|
|
} else if (b.low < a.low) {
|
|
aIsLargerSignificand = 1;
|
|
} else {
|
|
aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
|
|
}
|
|
|
|
if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
|
|
if (is_snan(b_cls)) {
|
|
return floatx80_silence_nan(b, status);
|
|
}
|
|
return b;
|
|
} else {
|
|
if (is_snan(a_cls)) {
|
|
return floatx80_silence_nan(a, status);
|
|
}
|
|
return a;
|
|
}
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------
|
|
| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
|
|
| NaN; otherwise returns 0.
|
|
*----------------------------------------------------------------------------*/
|
|
|
|
bool float128_is_quiet_nan(float128 a, float_status *status)
|
|
{
|
|
if (no_signaling_nans(status)) {
|
|
return float128_is_any_nan(a);
|
|
} else {
|
|
if (snan_bit_is_one(status)) {
|
|
return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
|
|
&& (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
|
|
} else {
|
|
return ((a.high << 1) >= 0xFFFF000000000000ULL)
|
|
&& (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
|
|
}
|
|
}
|
|
}
|
|
|
|
/*----------------------------------------------------------------------------
|
|
| Returns 1 if the quadruple-precision floating-point value `a' is a
|
|
| signaling NaN; otherwise returns 0.
|
|
*----------------------------------------------------------------------------*/
|
|
|
|
bool float128_is_signaling_nan(float128 a, float_status *status)
|
|
{
|
|
if (no_signaling_nans(status)) {
|
|
return 0;
|
|
} else {
|
|
if (snan_bit_is_one(status)) {
|
|
return ((a.high << 1) >= 0xFFFF000000000000ULL)
|
|
&& (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
|
|
} else {
|
|
return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
|
|
&& (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF)));
|
|
}
|
|
}
|
|
}
|