eb19d9079e
These memops perform interleave decoding, walking down the CXL topology from CFMWS described host interleave decoder via CXL host bridge HDM decoders, through the CXL root ports and finally call CXL type 3 specific read and write functions. Note that, whilst functional the current implementation does not support: * switches * multiple HDM decoders at a given level. * unaligned accesses across the interleave boundaries Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com> Message-Id: <20220429144110.25167-34-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
62 lines
1.3 KiB
C
62 lines
1.3 KiB
C
/*
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* QEMU CXL Support
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*
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* Copyright (c) 2020 Intel
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef CXL_H
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#define CXL_H
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#include "qapi/qapi-types-machine.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_host.h"
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#include "cxl_pci.h"
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#include "cxl_component.h"
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#include "cxl_device.h"
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#define CXL_COMPONENT_REG_BAR_IDX 0
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#define CXL_DEVICE_REG_BAR_IDX 2
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#define CXL_WINDOW_MAX 10
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typedef struct CXLFixedWindow {
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uint64_t size;
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char **targets;
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struct PXBDev *target_hbs[8];
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uint8_t num_targets;
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uint8_t enc_int_ways;
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uint8_t enc_int_gran;
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/* Todo: XOR based interleaving */
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MemoryRegion mr;
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hwaddr base;
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} CXLFixedWindow;
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typedef struct CXLState {
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bool is_enabled;
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MemoryRegion host_mr;
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unsigned int next_mr_idx;
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GList *fixed_windows;
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} CXLState;
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struct CXLHost {
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PCIHostState parent_obj;
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CXLComponentState cxl_cstate;
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};
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#define TYPE_PXB_CXL_HOST "pxb-cxl-host"
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OBJECT_DECLARE_SIMPLE_TYPE(CXLHost, PXB_CXL_HOST)
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void cxl_fixed_memory_window_config(MachineState *ms,
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CXLFixedMemoryWindowOptions *object,
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Error **errp);
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void cxl_fixed_memory_window_link_targets(Error **errp);
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extern const MemoryRegionOps cfmws_ops;
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#endif
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