Philippe Mathieu-Daudé 18f86aecd6 target/mips: Fix TX79 LQ/SQ opcodes ...

The base register address offset is *signed*.

Cc: qemu-stable@nongnu.org
Fixes: aaaa82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914090447.12557-1-philmd@linaro.org>

2023-11-07 12:13:28 +01:00

..

sysemu

hw/mips: Merge 'hw/mips/cpudevs.h' with 'target/mips/cpu.h'

2023-10-19 23:13:27 +02:00

tcg

target/mips: Fix TX79 LQ/SQ opcodes

2023-11-07 12:13:28 +01:00

cpu-defs.c.inc

hw/mips: spelling fixes

2023-08-31 19:47:43 +02:00

cpu-param.h

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cpu-qom.h

target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'

2023-11-07 12:13:27 +01:00

cpu.c

accel/tcg: Remove cpu_set_cpustate_pointers

2023-10-04 11:03:54 -07:00

cpu.h

target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'

2023-11-07 12:13:27 +01:00

fpu_helper.h

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fpu.c

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gdbstub.c

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helper.h

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internal.h

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Kconfig

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kvm_mips.h

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kvm.c

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meson.build

meson: Rename target_softmmu_arch -> target_system_arch

2023-10-07 19:03:07 +02:00

mips-defs.h

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msa.c

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