Max Filippov 2c09eee112 target-xtensa: add basic tests for cache opcodes ...

Test that non-locking prefetch operations don't cause exceptions on
missing TLB and that other 'hit' cache operations do.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

2014-02-24 04:47:02 +04:00

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alpha

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cris

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lm32

tests: lm32: new rule for single test cases

2014-02-04 19:34:29 +01:00

mips

target-mips: correct the values in the DSP tests

2013-07-30 17:48:24 +02:00

openrisc

target-openrisc: Correct carry flag check of l.addc and l.addic test cases

2013-11-20 21:47:46 +08:00

xtensa

target-xtensa: add basic tests for cache opcodes

2014-02-24 04:47:02 +04:00

hello-arm.c

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hello-i386.c

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hello-mips.c

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linux-test.c

remove some double-includes

2013-05-18 16:35:12 +04:00

Makefile

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pi_10.com

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runcom.c

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sha1.c

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test_path.c

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test-arm-iwmmxt.s

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test-i386-code16.S

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test-i386-fprem.c

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test-i386-muldiv.h

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test-i386-shift.h

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test-i386-ssse3.c

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test-i386-vm86.S

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test-i386.c

test-i386: make it compile with a recent gcc

2013-02-18 15:03:55 -08:00

test-i386.h

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test-mmap.c

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testthread.c

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