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a5158a963e
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Paolo Bonzini a5158a963e hexagon: do not specify executables as inputs 
gen_semantics is an executable, not an input.  Meson 0.57 special cases
the first argument and @INPUT@ is not expanded there.  Fix that by
not including it in the input, only in the command.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-04-01 10:37:20 +02:00
..
alpha cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass 2021-02-05 10:24:15 -10:00
arm target/arm: Make number of counters in PMCR follow the CPU 2021-03-30 14:05:33 +01:00
avr target/avr: Fix interrupt execution 2021-03-15 00:39:52 +01:00
cris target/cris: Plug leakage of TCG temporaries 2021-02-22 09:04:58 +01:00
hexagon hexagon: do not specify executables as inputs 2021-04-01 10:37:20 +02:00
hppa exec: Use cpu_untagged_addr in g2h; split out g2h_untagged 2021-02-16 11:04:53 +00:00
i386 target/i386: Verify memory operand for lcall and ljmp 2021-04-01 09:40:45 +02:00
lm32 semihosting: Move include/hw/semihosting/ -> include/semihosting/ 2021-03-10 15:34:12 +00:00
m68k Prepare MacOS ROM support: 2021-03-12 18:56:56 +00:00
microblaze cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass 2021-02-05 10:24:15 -10:00
mips target/mips/mxu_translate.c: Fix array overrun for D16MIN/D16MAX 2021-03-22 15:05:41 +01:00
moxie exec: Move TranslationBlock typedef to qemu/typedefs.h 2021-02-18 08:19:08 +00:00
nios2 semihosting: Move include/hw/semihosting/ -> include/semihosting/ 2021-03-10 15:34:12 +00:00
openrisc target/openrisc: fix icount handling for timer instructions 2021-04-01 10:37:20 +02:00
ppc target/ppc/kvm: Cache timebase frequency 2021-03-31 11:10:50 +11:00
riscv target/riscv: Prevent lost illegal instruction exceptions 2021-03-22 21:54:40 -04:00
rx cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass 2021-02-05 10:24:15 -10:00
s390x s390x: move S390_ADAPTER_SUPPRESSIBLE 2021-03-26 09:33:50 +01:00
sh4 target/sh4: Remove unused definitions 2021-03-06 16:18:42 +01:00
sparc cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass 2021-02-05 10:24:15 -10:00
tricore target/tricore: Fix OPC2_32_RRPW_EXTR for width=0 2021-03-14 14:49:01 +01:00
unicore32 semihosting: Move include/hw/semihosting/ -> include/semihosting/ 2021-03-10 15:34:12 +00:00
xtensa semihosting: Move include/hw/semihosting/ -> include/semihosting/ 2021-03-10 15:34:12 +00:00
meson.build Remove deprecated target tilegx 2021-03-09 11:26:32 +01:00